View MC68HC908LD64_741644.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC68HC908LD64
Data Sheet
M68HC08 Microcontrollers
MC68HC908LD64 Rev. 3.0 07/2004
freescale.com
MC68HC908LD64
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST.
(c) Freescale Semiconductor, Inc., 2004
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet 3
Revision History
Revision History
Date Revision Level Description Figure 13-2 . ADC Block Diagram -- Removed incorrect ADICLK input to clock generator in block diagram. 18.7.1 OSD Control Register (OSDCR) -- Corrected HALFCLK bit definitions. 18.7.2 OSD Status Register (OSDSR) -- Corrected WRDY bit description. July 2004 3 18.7.3 OSD Data Registers (OSDDRH:OSDDRL) -- Corrected OSDD[15:0] bits description. 18.8.3.5 Frame Control Registers -- Corrected OSD_EN bit location. Section 11. Timer Interface Module (TIM) -- Corrected timer discrepancies throughout. Section 16. DDC12AB Interface -- Changed the prefix "D" to "DDC" in DDC12AB register name abbreviations throughout. Page Number(s) 179 278 278 279 288 149 235
Data Sheet 4
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 31 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 61 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. Configuration Register (CONFIG) . . . . . . . . . 75 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 77 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . 95 Section 8. Clock Generator Module (CGM) . . . . . . . . . . . 99 Section 9. System Integration Module (SIM) . . . . . . . . 113 Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 137 Section 11. Timer Interface Module (TIM) . . . . . . . . . . . 149 Section 12. Pulse Width Modulator (PWM) . . . . . . . . . . 171 Section 13. Analog-to-Digital Converter (ADC) . . . . . . 177 Section 14. Universal Serial Bus Module (USB) . . . . . . 187 Section 15. Multi-Master IIC Interface (MMIIC) . . . . . . . 221 Section 16. DDC12AB Interface . . . . . . . . . . . . . . . . . . . 235 Section 17. Sync Processor . . . . . . . . . . . . . . . . . . . . . . 251 Section 18. On-Screen Display (OSD) . . . . . . . . . . . . . . 271 Section 19. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 293 Section 20. External Interrupt (IRQ) . . . . . . . . . . . . . . . 315 Section 21. Keyboard Interrupt Module (KBI). . . . . . . . 321 Section 22. Computer Operating Properly (COP) . . . . 329 Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . . 335 Section 24. Electrical Specifications. . . . . . . . . . . . . . . 343 Section 25. Mechanical Specifications . . . . . . . . . . . . . 357 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 359
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor List of Sections Data Sheet 5
List of Sections
Data Sheet 6 List of Sections
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 2. Memory Map
2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Section 3. Random-Access Memory (RAM)
3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 4. FLASH Memory
4.1 4.2
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Data Sheet 7
Table of Contents
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.4 FLASH Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.1 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . . 67 4.5 4.6 4.7 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 68 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 FLASH Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . 72
Section 5. Configuration Register (CONFIG)
5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 6. Central Processor Unit (CPU)
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7
Data Sheet 8 Table of Contents
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
6.8 6.9
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Section 7. Oscillator (OSC)
7.1 7.2 7.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .96
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 97 7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 97 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 97 7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 97 7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 98
Section 8. Clock Generator Module (CGM)
8.1 8.2 8.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.5 CGM I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 103 8.5.2 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 103 8.5.3 PLL Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 103 8.5.4 Crystal Output Frequency Signal (OSCXCLK). . . . . . . . . . 104 8.5.5 Crystal Reference Frequency Signal (OSCRCLK). . . . . . . 104 8.5.6 CGM Base Clock Output (DCLK1) . . . . . . . . . . . . . . . . . . . 104 8.5.7 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 104
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents Data Sheet 9
Table of Contents
8.6 CGM I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 106 8.6.3 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . 108 8.6.4 H & V Sync Output Control Register (HVOCR) . . . . . . . . . 110 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 112
Section 9. System Integration Module (SIM)
9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 117 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 117 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 119 9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 121 9.4.2.3 Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . .121 9.4.2.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.2.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 122 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 122 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 123 9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Data Sheet 10 Table of Contents
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
9.6.1.2 9.6.2 9.6.2.1 9.6.2.2 9.6.3 9.6.4 9.6.5
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 129 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 129 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 130
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 134 9.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 135 9.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 136
Section 10. Monitor ROM (MON)
10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Section 11. Timer Interface Module (TIM)
11.1 11.2 11.3 11.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Data Sheet 11
Table of Contents
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 154 11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .155 11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 155 11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 156 11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 157 11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.8 11.9 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 161 11.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 163 11.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 164 11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 165 11.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 168
Section 12. Pulse Width Modulator (PWM)
12.1 12.2 12.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.4.1 PWM Data Registers 0 to 7 (0PWM-7PWM). . . . . . . . . . . 173 12.4.2 PWM Control Register (PWMCR) . . . . . . . . . . . . . . . . . . . 174
Data Sheet 12 Table of Contents
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
Section 13. Analog-to-Digital Converter (ADC)
13.1 13.2 13.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.1 ADC Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . 182 13.7.2 ADC Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . .182 13.7.3 ADC Voltage Reference High Pin (VRH) . . . . . . . . . . . . . . 182 13.7.4 ADC Voltage Reference Low Pin (VRL). . . . . . . . . . . . . . . 182 13.7.5 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .183 13.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 185
Section 14. Universal Serial Bus Module (USB)
14.1 14.2 14.3 14.4 14.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Data Sheet 13
Table of Contents
14.6 Hub Function I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.6.1 USB Hub Root Port Control Register (HRPCR) . . . . . . . . . 194 14.6.2 USB Hub Downstream Port Control Registers (HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.6.3 USB SIE Timing Interrupt Register (SIETIR) . . . . . . . . . . . 198 14.6.4 USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . . 200 14.6.5 USB Hub Address Register (HADDR) . . . . . . . . . . . . . . . . 202 14.6.6 USB Hub Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . . 203 14.6.7 USB Hub Control Register 0 (HCR0) . . . . . . . . . . . . . . . . . 205 14.6.8 USB Hub Endpoint 1 Control and Data Register (HCDR) . 206 14.6.9 USB Hub Status Register (HSR) . . . . . . . . . . . . . . . . . . . . 208 14.6.10 USB Hub Endpoint 0 Data Registers (HE0D0-HE0D7). . . 209 14.7 Embedded Device Function I/O Registers . . . . . . . . . . . . . . . 209 14.7.1 USB Embedded Device Address Register (DADDR). . . . . 210 14.7.2 USB Embedded Device Interrupt Register 0 (DIR0) . . . . . 210 14.7.3 USB Embedded Device Interrupt Register 1 (DIR1) . . . . . 212 14.7.4 USB Embedded Device Control Register 0 (DCR0) . . . . . 213 14.7.5 USB Embedded Device Control Register 1 (DCR1) . . . . . 215 14.7.6 USB Embedded Device Control Register 2 (DCR2) . . . . . 216 14.7.7 USB Embedded Device Status Register (DSR) . . . . . . . . . 217 14.7.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.7.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Section 15. Multi-Master IIC Interface (MMIIC)
15.1 15.2 15.3 15.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . 224 15.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . 225 15.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . . 226 15.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . 228
Data Sheet 14 Table of Contents MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
15.5.5 15.5.6 15.6
Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . 230 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . 231 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 232
Section 16. DDC12AB Interface
16.1 16.2 16.3 16.4 16.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
16.6 DDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6.1 DDC Address Register (DDCADR) . . . . . . . . . . . . . . . . . . 238 16.6.2 DDC2 Address Register (DDC2ADR) . . . . . . . . . . . . . . . . 239 16.6.3 DDC Control Register (DDCCR) . . . . . . . . . . . . . . . . . . . . 240 16.6.4 DDC Master Control Register (DDCMCR) . . . . . . . . . . . . . 241 16.6.5 DDC Status Register (DDCSR) . . . . . . . . . . . . . . . . . . . . . 244 16.6.6 DDC Data Transmit Register (DDCDTR) . . . . . . . . . . . . . . 246 16.6.7 DDC Data Receive Register (DDCDRR) . . . . . . . . . . . . . . 247 16.7 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 248
Section 17. Sync Processor
17.1 17.2 17.3 17.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
17.5 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.5.1 Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.1 Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.2 Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.3 Composite Sync Polarity Detection . . . . . . . . . . . . . . . . 256 17.5.2 Sync Signal Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Data Sheet 15
Table of Contents
17.5.3 17.5.4 17.5.5 Polarity Controlled HOUT and VOUT Outputs . . . . . . . . . . 257 Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . . 259
17.6 Sync Processor I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . 259 17.6.1 Sync Processor Control & Status Register (SPCSR). . . . . 259 17.6.2 Sync Processor Input/Output Control Register (SPIOCR) . 261 17.6.3 Vertical Frequency Registers (VFRs). . . . . . . . . . . . . . . . . 263 17.6.4 Hsync Frequency Registers (HFRs). . . . . . . . . . . . . . . . . . 265 17.6.5 Sync Processor Control Register 1 (SPCR1). . . . . . . . . . . 267 17.6.6 H & V Sync Output Control Register (HVOCR) . . . . . . . . . 268 17.7 System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Section 18. On-Screen Display (OSD)
18.1 18.2 18.3 18.4 18.5 18.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 OSD FLASH Font Memory Map . . . . . . . . . . . . . . . . . . . . . . . 275 OSD Screen Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
18.7 OSD Module I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .277 18.7.1 OSD Control Register (OSDCR) . . . . . . . . . . . . . . . . . . . . 277 18.7.2 OSD Status Register (OSDSR) . . . . . . . . . . . . . . . . . . . . . 278 18.7.3 OSD Data Registers (OSDDRH:OSDDRL) . . . . . . . . . . . . 279 18.7.4 OSD Row Address Register (OSDRAR) . . . . . . . . . . . . . . 280 18.7.5 OSD Column Address Register (OSDCAR). . . . . . . . . . . . 280 18.7.6 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . 281 18.8 OSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.8.1 OSD Display Registers (Attribute and Code Registers) . . . 282 18.8.2 Row Attribute Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.8.3 Control, Window, and Pattern Registers . . . . . . . . . . . . . . 283 18.8.3.1 Window Registers 1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . 284 18.8.3.2 Vertical Delay Control Register . . . . . . . . . . . . . . . . . . . 285 18.8.3.3 Horizontal Delay Control Register . . . . . . . . . . . . . . . . . 286
Data Sheet 16 Table of Contents MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
18.8.3.4 18.8.3.5
Character Height Control Register . . . . . . . . . . . . . . . . . 286 Frame Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 288
Section 19. Input/Output (I/O) Ports
19.1 19.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
19.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 298 19.3.3 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 19.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.4.3 Port B Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.3 Port C Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.6.3 Port D Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.7.3 Port E Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Section 20. External Interrupt (IRQ)
20.1 20.2 20.3 20.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Data Sheet 17
Table of Contents
20.4.1 20.5 20.6 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 319 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 320
Section 21. Keyboard Interrupt Module (KBI)
21.1 21.2 21.3 21.4 21.5 21.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
21.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 326 21.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 327 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.9 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 328
Section 22. Computer Operating Properly (COP)
22.1 22.2 22.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
22.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Data Sheet 18 Table of Contents
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Table of Contents
22.4.7 22.4.8 22.5 22.6 22.7
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 332 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
22.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 334
Section 23. Break Module (BRK)
23.1 23.2 23.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 338 23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .338 23.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 338 23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 338 23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 339 23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 342
Section 24. Electrical Specifications
24.1 24.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Table of Contents
Data Sheet 19
Table of Contents
24.3 24.4 24.5 24.6 24.7 24.8 24.9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 345 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 346 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 347 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
24.10 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 348 24.11 Sync Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.12 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 349 24.12.1 USB Low Speed Source Electrical Characteristics . . . . . . 350 24.12.2 USB High Speed Source Electrical Characteristics . . . . . . 351 24.12.3 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . 352 24.12.4 USB Signaling Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24.13 DDC12AB/MMIIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 24.13.1 DDC12AB/MMIIC Interface Input Signal Timing . . . . . . . . 354 24.13.2 DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . 354 24.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 355
Section 25. Mechanical Specifications
25.1 25.2 25.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 64-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 358
Section 26. Ordering Information
26.1 26.2 26.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Data Sheet 20 Table of Contents
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
List of Figures
Figure 1-1 1-2 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 8-1 8-2 8-3 8-4
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor List of Figures
Title
Page
MC68HC908LD64 MCU Block Diagram. . . . . . . . . . . . . . . . . . 35 64-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .45 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64 47,616-byte FLASH Control Register (FLCR) . . . . . . . . . . . . . 66 13K-byte FLASH Control Register (FLCR1) . . . . . . . . . . . . . . . 66 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . . . . 67 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 71 47,616-byte FLASH Block Protect Register (FLBPR). . . . . . . . 72 13K-byte FLASH Block Protect Register 1 (FLBPR1) . . . . . . . 72 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .73 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . 76 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 82 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .96 CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 102 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 105 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 107
Data Sheet 21
List of Figures
Figure 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 10-1 10-2 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 Title Page
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . 108 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 110 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .116 OSC Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 126 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . 129 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . 129 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 132 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 132 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 133 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 134 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 135 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 136 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 156 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 161 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 163 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 164
Data Sheet 22 List of Figures
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
List of Figures
Figure
Title
Page
11-6 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 165 11-7 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11-8 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 169 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 PWM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 172 PWM Data Registers 0 to 7 (0PWM-7PWM) . . . . . . . . . . . . . 173 PWM Control Register (PWMCR). . . . . . . . . . . . . . . . . . . . . . 174 8-Bit PWM Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 175 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 178 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 183 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . . 185 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 190 USB Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 193 USB Hub Root Port Control Register (HRPCR) . . . . . . . . . . . 194 USB Hub Downstream Port Control Registers (HDP1CR-HDP4CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 USB SIE Timing Interrupt Register (SIETIR) . . . . . . . . . . . . . 198 USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . . . . 200 USB Hub Address Register (HADDR) . . . . . . . . . . . . . . . . . . 202 USB Hub Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . . . . 203 USB Hub Control Register 0 (HCR0) . . . . . . . . . . . . . . . . . . . 205 USB Hub Endpoint 1 Control and Data Register (HCDR) . . . 206 USB Hub Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 208 USB Hub Endpoint 0 Data Registers (HE0D0-HE0D7) . . . . . 209 USB Embedded Device Address Register (DADDR) . . . . . . . 210 USB Embedded Device Interrupt Register 0 (DIR0). . . . . . . . 210 USB Embedded Device Interrupt Register 1 (DIR1). . . . . . . . 212 USB Embedded Device Control Register 0 (DCR0). . . . . . . . 213 USB Embedded Device Control Register 1 (DCR1). . . . . . . . 215 USB Embedded Device Control Register 2 (DCR2). . . . . . . . 216 USB Embedded Device Status Register (DSR) . . . . . . . . . . . 217 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Data Sheet List of Figures 23
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
List of Figures
Figure Title Page
14-21 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 223 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 224 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 225 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 226 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 228 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 230 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 231 Data Transfer Sequences for Master/Slave Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DDC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 237 DDC Address Register (DDCADR). . . . . . . . . . . . . . . . . . . . . 238 DDC2 Address Register (DDC2ADR). . . . . . . . . . . . . . . . . . . 239 DDC Control Register (DDCCR). . . . . . . . . . . . . . . . . . . . . . . 240 DDC Master Control Register (DDCMCR) . . . . . . . . . . . . . . . 241 DDC Status Register (DDCSR) . . . . . . . . . . . . . . . . . . . . . . .244 DDC Data Transmit Register (DDCDTR) . . . . . . . . . . . . . . . . 246 DDC Data Receive Register (DDCDRR) . . . . . . . . . . . . . . . . 247 Data Transfer Sequences for Master/Slave Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Sync Processor I/O Register Summary . . . . . . . . . . . . . . . . . 254 Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . .255 Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Sync Processor Control & Status Register (SPCSR) . . . . . . . 259 Sync Processor Input/Output Control Register (SPIOCR) . . . 261 Vertical Frequency High Register . . . . . . . . . . . . . . . . . . . . . . 263 Vertical Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . 263 Hsync Frequency High Register . . . . . . . . . . . . . . . . . . . . . . . 265 Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .265 Sync Processor Control Register 1 (SPCR1) . . . . . . . . . . . . . 267 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 268
16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9
17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11
Data Sheet 24 List of Figures
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
List of Figures
Figure 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20
Title
Page
On-Screen Display I/O Register Summary . . . . . . . . . . . . . . . 273 OSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Memory Map of OSD FLASH Fonts . . . . . . . . . . . . . . . . . . . .275 Memory Map of OSD Registers . . . . . . . . . . . . . . . . . . . . . . .276 OSD Control Register (OSDCR). . . . . . . . . . . . . . . . . . . . . . . 277 OSD Status Register (OSDSR) . . . . . . . . . . . . . . . . . . . . . . .278 OSD Data Register High (OSDDRH) . . . . . . . . . . . . . . . . . . . 279 OSD Data Register Low (OSDDRL) . . . . . . . . . . . . . . . . . . . .279 OSD Row Address Register (OSDRAR) . . . . . . . . . . . . . . . . 280 OSD Column Address Register (OSDCAR) . . . . . . . . . . . . . . 280 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . . . 281 OSD Font Even Byte Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Character Font Matrix Height Expansion by CH[3:0] . . . . . . . 287 Display Character Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Port I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .294 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 298 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Keyboard Interrupt Enable Register (KIER) . . . . . . . . . . . . . . 299 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 301 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 PWM Control Register (PWMCR). . . . . . . . . . . . . . . . . . . . . . 302 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 304 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 307 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . 309 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 312 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Port E Control Register (PECR) . . . . . . . . . . . . . . . . . . . . . . . 313
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor List of Figures
Data Sheet 25
List of Figures
Figure Title Page
20-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .317 20-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 319 21-1 21-2 21-3 21-4 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Keyboard Interrupt Module Block Diagram. . . . . . . . . . . . . . . 323 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 326 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 327
22-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 22-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . 332 22-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 333 23-1 23-2 23-3 23-4 23-5 23-6 23-7 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 337 Break Module I/O Register Summary . . . . . . . . . . . . . . . . . . . 337 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 339 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 340 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 340 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 341 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 342
24-1 MMIIC Signal Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 25-1 64-Pin QFP (Case #840B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Data Sheet 26 List of Figures
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
List of Tables
Table 1-1 2-1 4-1 6-1 6-2 8-1 8-2 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9
Title
Page
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 FLASH Memory Array Summary . . . . . . . . . . . . . . . . . . . . . . . 65 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Free-Running HSOUT, VSOUT, DE, and DCLK Settings . . . 102 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . . 109 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SIM Registers Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Monitor Mode Signal Requirements and Options . . . . . . . . . . 141 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 144 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 145 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 145 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 146 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 146 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 147 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 147
11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 167
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor List of Tables Data Sheet 27
List of Tables
Table Title Page
12-1 PWM Channels and Port I/O pins. . . . . . . . . . . . . . . . . . . . . . 174 13-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 14-1 USB I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15-2 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16-2 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Sync Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Sync Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 ATPOL, VINVO, and HINVO setting. . . . . . . . . . . . . . . . . . . .261 Sample Vertical Frame Frequencies . . . . . . . . . . . . . . . . . . . 264 Clamp Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 HSYNC Polarity Detection Pulse Width . . . . . . . . . . . . . . . . . 267 ATPOL, VINVO, and HINVO setting. . . . . . . . . . . . . . . . . . . .268 Free-Running HSOUT, VSOUT, DE, and DCLK Settings . . . 269
18-1 Shadow Width Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 18-2 Shadow Width Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 19-1 19-2 19-3 19-4 19-5 19-6 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .296 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
21-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 24-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Data Sheet 28 List of Tables
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
List of Tables
Table 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 24-16 24-17
Title
Page
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 346 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 TIM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 348 Sync Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 349 USB Low Speed Source Electrical Characteristics. . . . . . . . . 350 USB High Speed Source Electrical Characteristics . . . . . . . . 351 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . . 352 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 DDC12AB/MMIIC Interface Input Signal Timing. . . . . . . . . . . 354 DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . . . 354 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 355
26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor List of Tables
Data Sheet 29
List of Tables
Data Sheet 30 List of Tables
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.2 Introduction
The MC68HC908LD64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. With special modules such as the sync processor, on-screen display module, analog-to-digital converter, pulse modulator module, DDC12AB interface, multi-master IIC interface, and universal serial bus interface, the MC68HC908LD64 is designed specifically for use in digital monitor systems.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor General Description
Data Sheet 31
General Description 1.3 Features
Features of the MC68HC908LD64 MCU include the following: * * * * * * * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 families Low-power design; fully static with stop and wait modes 3.3V operating voltage 6MHz internal bus frequency; with 24MHz external crystal 60,928 bytes of on-chip FLASH memory with security1 feature 2,048 bytes of on-chip random access memory (RAM) 39 general-purpose input/output (I/O) pins, including: - 38 shared-function I/O pins - 8-bit keyboard interrupt port * 2-channel, 16-bit timer interface module (TIM) with selectable input capture, output compare, and PWM capability on one channel 6-channel, 8-bit analog-to-digital converter (ADC) 8-channel, 8-bit pulse width modulator (PWM) Sync signal processor with the following features: - Horizontal and vertical frequency counters - Low vertical frequency indicator (40.7Hz) - Polarity controlled Hsync and Vsync outputs from separate sync or composite sync inputs - Internal generated free-running Hsync, Vsync, DE, and DCLK - CLAMP pulse output to the external pre-amp chip * On screen display (OSD) and full screen pattern display
* * *
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Data Sheet 32 General Description
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
General Description Features
*
Full Universal Serial Bus (USB) specification 1.1, composite hub with embedded functions, including: - One 12MHz upstream port - Four 12MHz/1.5MHz downstream ports - One hub control endpoint with 8-byte transmit buffer and 8-byte receive buffer - One hub interrupt endpoint with 1-byte transmit buffer - One device control endpoint with 8-byte transmit buffer and 8-byte receive buffer - Two device interrupt endpoints with shared 8-byte transmit buffer
*
DDC12AB1 module with the following: - DDC1 hardware - Multi-master IIC2 hardware for DDC2AB; with dual address
* * *
Additional multi-master IIC module In-system programming capability using USB or DDC12AB communication, or standard serial link on PTA0 pin System protection features: - Optional computer operating properly (COP) reset - Illegal opcode detection with reset - Illegal address detection with reset
* * *
Master reset pin (with internal pull-up) and power-on reset IRQ interrupt pin with internal pull-up and schmitt-trigger input 64-pin quad flat pack (QFP) package
1. DDC is a VESA bus standard. 2. IIC is a proprietary Philips interface bus.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor General Description
Data Sheet 33
General Description
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Third party C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908LD64.
Data Sheet 34 General Description
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
General Description MCU Block Diagram
INTERNAL BUS M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PULSE WIDTH MODULATOR MODULE PORTB MONITOR MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE FREE-RUN PANEL TIMING MODULE PORTC DDRC PTB7/PWM7 : PTB0/PWM0 DDRB PORTA PTA7/KBI7 : PTA0/KBI0
CONTROL AND STATUS REGISTERS -- 80 BYTES USER FLASH -- 60,928 BYTES USER RAM -- 2,048 BYTES MONITOR ROM -- 1,024+464 BYTES USER FLASH VECTOR SPACE -- 32 BYTES CLOCK GENERATOR MODULE OSC1 OSC2 CGMXFC 24-MHz OSCILLATOR
PTC6 PTC5/ADC5 : PTC0/ADC0
SYNC PROCESSOR MODULE PHASE-LOCKED LOOP 2-CHANNEL TIMER INTERFACE MODULE MULTI-MASTER IIC INTERFACE MODULE DDC12AB INTERFACE MODULE MONITOR MODE ENTRY MODULE SECURITY MODULE DS PORT 4 UNIVERSAL SERIAL BUS INTERFACE MODULE AND HUB CONTROLLER POWER Pin is +5V open-drain Pin is +5V input DS PORT 3 DS PORT 2 DS PORT 1 US PORT PORTE DDRE
HSYNC VSYNC CLAMP/TCH0
RST
SYSTEM INTEGRATION MODULE EXTERNAL IRQ MODULE COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE
IRQ
PTD7/IICSDA PTD6/IICSCL PTD5/DDCSDA PTD4/DDCSCL PTD3/HOUT PTD2/VOUT PTD1/DE PTD0/DCLK
PHSYNC PVSYNC PCLK OSDR OSDG OSDB FBKG VDD1 VSS1 VDD2 VSS2 VDDA VSSA VRH VRL
PORTD
DDRD
ON-SCREEN DISPLAY MODULE
PTE7/DMINUS4 PTE6/DPLUS4 PTE5/DMINUS3 PTE4/DPLUS3 PTE3/DMINUS2 PTE2/DPLUS2 PTE1/DMINUS1 PTE0/DPLUS1 DMINUS0 DPLUS0
ADC REFERENCE
Figure 1-1. MC68HC908LD64 MCU Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor General Description
Data Sheet 35
General Description 1.5 Pin Assignments
PTC0/ADC0
PTC1/ADC1
PTC2/ADC2
PTC3/ADC3
PTC4/ADC4
PTC5/ADC5
PTA7/KBI7
PTA6/KBI6
PTA5/KBI5
50
64
63
62
61
60
59
58
57
56
55
54
53
52
VDDA OSC1 OSC2 VSSA VDD1 DPLUS0 DMINUS0 PTE0/DPLUS1 PTE1/DMINUS1 PTE2/DPLUS2 PTE3/DMINUS2 PTE4/DPLUS3 PTE5/DMINUS3 PTE6/DPLUS4 PTE7/DMINUS4
51
49
PTA4/KBI4
VSS2
PTC6
VRH
RST
VRL
IRQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
PTA3/KBI3 PTA2/KBI2 PTA1/KBI1 PTA0/KBI0 VDD2 PTB7/PWM7 PTB6/PWM6 PTB5/PWM5 PTB4/PWM4 PTB3/PWM3 PTB2/PWM2 PTB1/PWM1 PTB0/PWM0 PTD7IICSDA PTD6/IICSCL
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS1 17
31
CGMXFC 16
33
PTD5/DDCSDA
Figure 1-2. 64-Pin QFP Pin Assignment
Data Sheet 36 General Description
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
PTD4/DDCSCL 32
OSDG
CLAMP/TCH0
OSDB
PTD0/DCLK
FBKG
PTD1/DE
VSYNC
PCLK
PTD2/VOUT
PVSYNC
PHSYNC
HSYNC
OSDR
PTD3/HOUT
General Description Pin Functions
1.6 Pin Functions
Description of the pin functions are provided in Table 1-1. Table 1-1. Pin Functions
PIN NAME VDD1, VDD2 VSS1, VSS2 VDDA VSSA PIN DESCRIPTION Power supply input to the MCU. Power supply ground. Power supply input for analog circuits. Power supply ground for analog circuits. Crystal connections to the on-chip oscillator. An external clock can be connected directly to OSC1; with OSC2 floating. See Section 7. Oscillator (OSC). External reset pin; active low; with internal pull-up and schmitt trigger input. It is driven low when any internal reset source is asserted. See Section 9. System Integration Module (SIM). External IRQ pin; with schmitt trigger input and internal pull-up. This pin is also used for mode entry selection. See Section 20. External Interrupt (IRQ) and Section 9. System Integration Module (SIM). External filter capacitor connection for the CGM module. See Section 8. Clock Generator Module (CGM). Vsync input to the sync processor. This pin is rated at +5V. See Section 17. Sync Processor. Hsync input to the sync processor. This pin is rated at +5V. See Section 17. Sync Processor. These are shared function, bidirectional I/O port pins. Each pin contains a pull-up device to VDD when it is configured as an external keyboard interrupt pin. See Section 19. Input/Output (I/O) Ports and Section 21. Keyboard Interrupt Module (KBI).
OSC1, OSC2
RST
IRQ
CGMXFC
VSYNC
HSYNC
PTA7/KBI7-PTA0/KBI0
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor General Description
Data Sheet 37
General Description
Table 1-1. Pin Functions (Continued)
PIN NAME PIN DESCRIPTION These are shared-function, bidirectional I/O port pins. Each pin can be configured as a standard I/O pin or a PWM output channel. See Section 19. Input/Output (I/O) Ports and Section 12. Pulse Width Modulator (PWM). High voltage reference input to ADC module. Low voltage reference input to ADC module. This pin is a standard bidirectional I/O pin. See Section 19. Input/Output (I/O) Ports. These are shared-function, bidirectional I/O port pins. Each pin can be configured as a standard I/O pin or an ADC input channel. See Section 19. Input/Output (I/O) Ports and Section 13. Analog-to-Digital Converter (ADC). This is a shared-function pin. It can be configured as a standard I/O pin or the data line of the multimaster IIC module. This pin is +5V open-drain when configured as output. See Section 19. Input/Output (I/O) Ports and Section 15. Multi-Master IIC Interface (MMIIC). This is a shared function pin. It can be configured as a standard I/O pin or the clock line of the multimaster IIC module. This pin is +5V open-drain when configured as output. See Section 19. Input/Output (I/O) Ports and Section 15. Multi-Master IIC Interface (MMIIC). This is a shared function pin. It can be configured as a standard I/O pin or the data line of the DDC12AB module. This pin is +5V open-drain when configured as output. See Section 19. Input/Output (I/O) Ports and Section 16. DDC12AB Interface. This is a shared function pin. It can be configured as a standard I/O pin or the clock line of the DDC12AB module. This pin is +5V open-drain when configured as output. See Section 19. Input/Output (I/O) Ports and Section 16. DDC12AB Interface.
PTB7/PWM7-PTB0/PWM0
VRH VRL PTC6
PTC5/ADC5-PTC0/ADC0
PTD7/IICSDA
PTD6/IICSCL
PTD5/DDCSDA
PTD4/DDCSCL
Data Sheet 38 General Description
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
General Description Pin Functions
Table 1-1. Pin Functions (Continued)
PIN NAME PTD3/HOUT PTD2/VOUT PTD1/DE PTD0/DCLK PIN DESCRIPTION These are shared function, bidirectional I/O port pins. These pins can be configured as standard I/O pins or free-run timing output signals. See Section 19. Input/Output (I/O) Ports and Section 17. Sync Processor. This is shared function pins. This TIM channel 0 I/O pin can be configured as the Sync processor CLAMP output pin. See Section 11. Timer Interface Module (TIM) and Section 17. Sync Processor. Vsync input to the On-Screen Display module. This pin is rated at +5V. See Section 18. On-Screen Display (OSD). Hsync input to the On-Screen Display module. This pin is rated at +5V. See Section 18. On-Screen Display (OSD). Pixel clock input to the On-Screen Display module. This pin is rated at +5V. See Section 18. On-Screen Display (OSD). R, G, and B output of the On-Screen Display module. See Section 18. On-Screen Display (OSD). Pixel-enable output of the On-Screen Display module. See Section 18. On-Screen Display (OSD).
CLAMP/TCH0
PVSYNC
PHSYNC
PCLK OSDR OSDG OSDB FBKG PTE7/DMINUS4 PTE6/DPLUS4 PTE5/DMINUS3 PTE4/4DPLUS3 PTE3/DMINUS2 PTE2/DPLUS2 PTE1/DMINUS1 PTE0/DPLUS1 DPLUS0 DMINUS0
These are shared function, bidirectional I/O port pins. These pins can be configured as standard I/O pins or downstream data pins of USB module. See Section 19. Input/Output (I/O) Ports and Section 14. Universal Serial Bus Module (USB).
Data pins of USB module upstream port. See Section 14. Universal Serial Bus Module (USB).
NOTE:
Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC908LD64 do not require termination, termination is recommended to reduce the possibility of static damage.
Data Sheet General Description 39
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
General Description
Data Sheet 40 General Description
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 2. Memory Map
2.1 Contents
2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2 Introduction
The CPU08 can address 64K-bytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * 60,928 bytes of FLASH memory 2,048 bytes of random-access memory (RAM) 32 bytes of user-defined vectors 1,024 + 464 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 41
Memory Map 2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000-$007F. Additional I/O registers have these addresses: * * * * * * * * * * * * * * * * * $FE00; SIM break status register, SBSR $FE01; SIM reset status register, SRSR $FE02; Reserved $FE03; SIM break flag control register, SBFCR $FE04; Interrupt status register 1, INT1 $FE05; Interrupt status register 2, INT2 $FE06; Reserved $FE07; 47,616 bytes FLASH control register, FLCR $FE08; 47,616 bytes FLASH block protect register, FLBPR $FE09; Reserved $FE0A; 13K-bytes FLASH control register, FLCR1 $FE0B; 13K-bytes FLASH block protect register, FLBPR1 $FE0C; Break address register high, BRKH $FE0D; Break address register low, BRKL $FE0E; Break status and control register, BRKSCR $FE0F; Reserved $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
Data Sheet 42 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
$0000 $007F $0080 $047F $0480 $07FF $0800 $0BFF $0C00 $0FFF $1000 $3FFF $4000 $F9FF $FA00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) Reserved SIM Break Flag Control Register (SBFCR) Interrupt Status Register 1 (INT1) Monitor ROM 1,024 Bytes FLASH Memory 1,024 Bytes (8 x 128-Byte Blocks) OSD RAM 1,024 Bytes Unimplemented 896 Bytes RAM 1,024 Bytes I/O Registers 128 Bytes
OSD FLASH Memory 12,288 Bytes (24 x 512-Byte Blocks)
FLASH Memory 47,616 Bytes (93 x 512-Byte Blocks)
Figure 2-1. Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 43
Memory Map
$FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFDF $FFE0 $FFFF
Interrupt Status Register 2 (INT2) Reserved 47,616 bytes FLASH Control Register (FLCR) 47,616 bytes FLASH Block Protect Register (FLBPR) Reserved 13K-bytes FLASH Control Register (FLCR1) 13K-bytes FLASH Block Protect Register (FLBPR1) Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status and Control Register (BRKSCR) Reserved Monitor ROM 464 Bytes
FLASH Vectors 32 Bytes
Figure 2-1. Memory Map (Continued)
Data Sheet 44 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $0000
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 PTE6 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 PTE5 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0
Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0 Read: DDRB7 Data Direction Register B $0005 Write: (DDRB) Reset: 0 Read: Data Direction Register C $0006 Write: (DDRC) Reset: 0 0
Read: DDRD7 Data Direction Register D Write: $0007 (DDRD) Reset: 0 $0008 Read: Port E Data Register Write: (PTE) Reset: PTE7
Unaffected by reset DDRE6 0 DDRE5 0 DDRE4 0 DDRE3 0 DDRE2 0 R DDRE1 0 = Reserved DDRE0 0
Read: DDRE7 Data Direction Register E Write: $0009 (DDRE) Reset: 0 U = Unaffected
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 45
Memory Map
Addr. $000A
Register Name Read: TIM Status and Control Register Write: (TSC) Reset: Read: Unimplemented Write: Reset:
Bit 7 TOF 0 0
6 TOIE 0
5 TSTOP 1
4 0 TRST 0
3 0 0
2 PS2 0
1 PS1 0
Bit 0 PS0 0
$000B
0 Bit15 0 Bit7 0 Bit15 1 Bit7 1 CH0F 0 0 Bit15
0 Bit14 0 Bit6 0 Bit14 1 Bit6 1 CH0IE 0 Bit14
0 Bit13 0 Bit5 0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 0 Bit4 0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 0 Bit3 0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 0 Bit2 0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 0 Bit1 0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 0 Bit0 0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
Read: TIM Counter Register High $000C Write: (TCNTH) Reset: Read: TIM Counter Register Low $000D Write: (TCNTL) Reset: $000E TIM Counter Modulo Read: Register High Write: (TMODH) Reset: TIM Counter Modulo Read: Register Low Write: (TMODL) Reset: TIM Channel 0 Read: Status and Control Write: Register (TSC0) Reset: Read: TIM Channel 0 Register High Write: (TCH0H) Reset: TIM Channel 0 Read: Register Low Write: (TCH0L) Reset: TIM Channel 1 Read: Status and Control Write: Register (TSC1) Reset: U = Unaffected
$000F
$0010
$0011
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0012
Indeterminate after reset CH1F 0 0 CH1IE 0 0 MS1A 0 ELS1B 0 ELS1A 0 TOV1 0 CH1MAX 0
$0013
0
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 15)
Data Sheet 46 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $0014
Register Name Read: TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset: Read: DDC Master Control Register Write: (DDCMCR) Reset: Read: DDC Address Register Write: (DDCADR) Reset: Read: DDC Control Register Write: (DDCCR) Reset: Read: DDC Status Register Write: (DDCSR) Reset: DDC Data Transmit Read: Register Write: (DDCDTR) Reset: DDC Data Receive Read: Register Write: (DDCDRR) Reset:
Bit 7 Bit15
6 Bit14
5 Bit13
4 Bit12
3 Bit11
2 Bit10
1 Bit9
Bit 0 Bit8
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0015
Indeterminate after reset ALIF 0 DAD7 1 DEN 0 RXIF 0 0 DTD7 1 DRD7 NAKIF 0 DAD6 0 DIEN 0 TXIF 0 0 DTD6 1 DRD6 0 DTD5 1 DRD5 0 DTD4 1 DRD4 1 DTD3 1 DRD3 BB 0 DAD5 1 0 0 MATCH MAST 0 DAD4 0 0 0 SRW MRW 0 DAD3 0 TXAK 0 RXAK BR2 0 DAD2 0 SCLIEN 0 SCLIF 0 0 DTD2 1 DRD2 1 DTD1 1 DRD1 0 DTD0 1 DRD0 BR1 0 DAD1 0 DDC1EN 0 TXBE BR0 0 EXTAD 0 0 0 RXBF
$0016
$0017
$0018
$0019
$001A
$001B
0
0 D2AD6 0
0 D2AD5 0
0 D2AD4 0
0 D2AD3 0
0 D2AD2 0
0 D2AD1 0
0 0 0
$001C
Read: D2AD7 DDC2 Address Register Write: (DDC2ADR) Reset: 0 Read: Unimplemented Write: Reset: U = Unaffected
$001D
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 47
Memory Map
Addr. $001E
Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Read: Configuration Register Write: (CONFIG) Reset:
Bit 7 0 0 0 0
6 0 0 0 0 DE0R06 DE0T06 DE0R16 DE0T16 DE0R26 DE0T26 DE0R36 DE0T36 DE0R46 DE0T46 DE0R56 DE0T56 DE0R66 DE0T66 DE0R76 DE0T76
5 0 0 0 0 DE0R05 DE0T05 DE0R15 DE0T15 DE0R25 DE0T25 DE0R35 DE0T35 DE0R45 DE0T45 DE0R55 DE0T55 DE0R65 DE0T65 DE0R75 DE0T75
4 0 0 0 0 DE0R04 DE0T04 DE0R14 DE0T14 DE0R24 DE0T24 DE0R34 DE0T34 DE0R44 DE0T44 DE0R54 DE0T54 DE0R64 DE0T64 DE0R74 DE0T74
3 IRQF 0 SSREC 0 DE0R03 DE0T03 DE0R13 DE0T13 DE0R23 DE0T23 DE0R33 DE0T33 DE0R43 DE0T43 DE0R53 DE0T53 DE0R63 DE0T63 DE0R73 DE0T73
2 0 ACK 0 COPRS 0 DE0R02 DE0T02 DE0R12 DE0T12 DE0R22 DE0T22 DE0R32 DE0T32 DE0R42 DE0T42 DE0R52 DE0T52 DE0R62 DE0T62 DE0R72 DE0T72
1 IMASK 0 STOP 0 DE0R01 DE0T01 DE0R11 DE0T11 DE0R21 DE0T21 DE0R31 DE0T31 DE0R41 DE0T41 DE0R51 DE0T51 DE0R61 DE0T61 DE0R71 DE0T71
Bit 0 MODE 0 COPD 0 DE0R00 DE0T00 DE0R10 DE0T10 DE0R20 DE0T20 DE0R30 DE0T30 DE0R40 DE0T40 DE0R50 DE0T50 DE0R60 DE0T60 DE0R70 DE0T70
$001F
One-time writable register after each reset. $0020 Read: DE0R07 USB Embedded Device Endpoint 0 Data Reg. 0 Write: DE0T07 (DE0D0) Reset: Read: DE0R17 USB Embedded Device Endpoint 0 Data Reg. 1 Write: DE0T17 (DE0D1) Reset: Read: DE0R27 USB Embedded Device Endpoint 0 Data Reg. 2 Write: DE0T27 (DE0D2) Reset: Read: DE0R37 USB Embedded Device Endpoint 0 Data Reg. 3 Write: DE0T37 (DE0D3) Reset: Read: DE0R47 USB Embedded Device Endpoint 0 Data Reg. 4 Write: DE0T47 (DE0D4) Reset: USB Embedded Device Read: DE0R57 Endpoint 0 Data Reg. 5 Write: DE0T57 (DE0D5) Reset: USB Embedded Device Read: DE0R67 Endpoint 0 Data Reg. 6 Write: DE0T67 (DE0D6) Reset: USB Embedded Device Read: DE0R77 Endpoint 0 Data Reg. 7 Write: DE0T77 (DE0D7) Reset: U = Unaffected
Indeterminate after reset
$0021
Indeterminate after reset
$0022
Indeterminate after reset
$0023
Indeterminate after reset
$0024
Indeterminate after reset
$0025
Indeterminate after reset
$0026
Indeterminate after reset
$0027
Indeterminate after reset = Unimplemented R = Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 15)
Data Sheet 48 Memory Map MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6 DE1T06
5 DE1T05
4 DE1T04
3 DE1T03
2 DE1T02
1 DE1T01
Bit 0 DE1T00
Read: USB Embedded Device $0028 Endpoint 1/2 Data Reg. 0 Write: DE1T07 (DE1D0) Reset: Read: USB Embedded Device $0029 Endpoint 1/2 Data Reg. 1 Write: DE1T17 (DE1D1) Reset: Read: USB Embedded Device $002A Endpoint 1/2 Data Reg. 2 Write: DE1T27 (DE1D2) Reset: USB Embedded Device Read: $002B Endpoint 1/2 Data Reg. 3 Write: DE1T37 (DE1D3) Reset: USB Embedded Device Read: $002C Endpoint 1/2 Data Reg. 4 Write: DE1T47 (DE1D4) Reset: USB Embedded Device Read: $002D Endpoint 1/2 Data Reg. 5 Write: DE1T57 (DE1D5) Reset: USB Embedded Device Read: $002E Endpoint 1/2 Data Reg. 6 Write: DE1T67 (DE1D6) Reset: Read: USB Embedded Device $002F Endpoint 1/2 Data Reg. 7 Write: DE1T77 (DE1D7) Reset: $0030 Read: HE0R07 USB HUB Endpoint 0 Data Register 0 Write: HE0T07 (HE0D0) Reset: Read: HE0R17 USB HUB Endpoint 0 Data Register 1 Write: HE0T17 (HE0D1) Reset: U = Unaffected
Indeterminate after reset DE1T16 DE1T15 DE1T14 DE1T13 DE1T12 DE1T11 DE1T10
Indeterminate after reset DE1T26 DE1T25 DE1T24 DE1T23 DE1T22 DE1T21 DE1T20
Indeterminate after reset DE1T36 DE1T35 DE1T34 DE1T33 DE1T32 DE1T31 DE1T30
Indeterminate after reset DE1T46 DE1T45 DE1T44 DE1T43 DE1T42 DE1T41 DE1T40
Indeterminate after reset DE1T56 DE1T55 DE1T54 DE1T53 DE1T52 DE1T51 DE1T50
Indeterminate after reset DE1T66 DE1T65 DE1T64 DE1T63 DE1T62 DE1T61 DE1T60
Indeterminate after reset DE1T76 HE0R06 HE0T06 HE0R16 HE0T16 DE1T75 HE0R05 HE0T05 HE0R15 HE0T15 DE1T74 HE0R04 HE0T04 HE0R14 HE0T14 DE1T73 HE0R03 HE0T03 HE0R13 HE0T13 DE1T72 HE0R02 HE0T02 HE0R12 HE0T12 DE1T71 HE0R01 HE0T01 HE0R11 HE0T11 DE1T70 HE0R00 HE0T00 HE0R10 HE0T10
Indeterminate after reset
Indeterminate after reset
$0031
Indeterminate after reset = Unimplemented R = Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 49
Memory Map
Addr. $0032
Register Name
Bit 7
6 HE0R26 HE0T26 HE0R36 HE0T36 HE0R46 HE0T46 HE0R56 HE0T56 HE0R66 HE0T66 HE0R76 HE0T76 PLLF 0 LOCK 0 MUL6 1 AIEN 0
5 HE0R25 HE0T25 HE0R35 HE0T35 HE0R45 HE0T45 HE0R55 HE0T55 HE0R65 HE0T65 HE0R75 HE0T75
4 HE0R24 HE0T24 HE0R34 HE0T34 HE0R44 HE0T44 HE0R54 HE0T54 HE0R64 HE0T64 HE0R74 HE0T74
3 HE0R23 HE0T23 HE0R33 HE0T33 HE0R43 HE0T43 HE0R53 HE0T53 HE0R63 HE0T63 HE0R73 HE0T73 1 1 0 0 VRS7 0 ADCH3 1
2 HE0R22 HE0T22 HE0R32 HE0T32 HE0R42 HE0T42 HE0R52 HE0T52 HE0R62 HE0T62 HE0R72 HE0T72 1 1 0 0 VRS6 1 ADCH2 1 R
1 HE0R21 HE0T21 HE0R31 HE0T31 HE0R41 HE0T41 HE0R51 HE0T51 HE0R61 HE0T61 HE0R71 HE0T71 1 1 0 0 VRS5 1 ADCH1 1 = Reserved
Bit 0 HE0R20 HE0T20 HE0R30 HE0T30 HE0R40 HE0T40 HE0R50 HE0T50 HE0R60 HE0T60 HE0R70 HE0T70 1 1 0 0 VRS4 0 ADCH0 1
Read: HE0R27 USB HUB Endpoint 0 Data Register 2 Write: HE0T27 (HE0D2) Reset: Read: HE0R37 USB HUB Endpoint 0 Data Register 3 Write: HE0T37 (HE0D3) Reset: Read: HE0R47 USB HUB Endpoint 0 Data Register 4 Write: HE0T47 (HE0D4) Reset: USB HUB Endpoint 0 Read: HE0R57 Data Register 5 Write: HE0T57 (HE0D5) Reset: USB HUB Endpoint 0 Read: HE0R67 Data Register 6 Write: HE0T67 (HE0D6) Reset: USB HUB Endpoint 0 Read: HE0R77 Data Register 7 Write: HE0T77 (HE0D7) Reset: Read: PLL Control Register Write: (PCTL) Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Programming Register Write: (PPG) Reset: Read: ADC Status and Control Register Write: (ADSCR) Reset: U = Unaffected PLLIE 0 AUTO 0 MUL7 0 COCO 0
Indeterminate after reset
$0033
Indeterminate after reset
$0034
Indeterminate after reset
$0035
Indeterminate after reset
$0036
Indeterminate after reset
$0037
Indeterminate after reset PLLON 1 ACQ 0 MUL5 1 ADCO 0 BCS 0 XLD 0 MUL4 0 ADCH4 1
$0038
$0039
$003A
$003B
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 15)
Data Sheet 50 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $003C
Register Name Read: ADC Data Register Write: (ADR) Reset:
Bit 7 AD7
6 AD6
5 AD5
4 AD4
3 AD3
2 AD2
1 AD1
Bit 0 AD0
Indeterminate after reset ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0 0 0 0 0 0
Read: ADC Input Clock Register $003D Write: (ADICLK) Reset: Read: $003E Unimplemented Write: Reset: H & V Sync Output Control Read: $003F Register Write: (HVOCR) Reset: $0040 Sync Processor Control Read: and Status Register Write: (SPCSR) Reset: Vertical Frequency High Read: Register Write: (VFHR) Reset: Vertical Frequency Low Read: Register Write: (VFLR) Reset: Read: Hsync Frequency High Register Write: (HFHR) Reset:
DCLKPH1 DCLKPH0 0 VSIE 0 VOF 0 VF7 0 HFH7 0 VEDGE 0 0 CPW1 0 VF6 0 HFH6 0 0 0 VSIF 0 0 0 CPW0 0 VF5 0 HFH5 0 0 0 COINV 0 = Unimplemented 0 VF4 0 HFH4 0 HFL4 0 R 0 VF3 0 HFH3 0 HFL3 0 R COMP 0 VF12 0 VINVO 0 VF11
R
HVOCR1 HVOCR0 0 0 HPOL 0 VF8 0 VF0 0 HFH0 0 HFL0 0 SOUT 0
HINVO 0 VF10 0 VF2 0 HFH2 0 HFL2 0 R
VPOL 0 VF9 0 VF1 0 HFH1 0 HFL1 0 BPOR 0
$0041
$0042
$0043
$0044
Read: HOVER Hsync Frequency Low Register Write: (HFLR) Reset: 0
Read: VSYNCS HSYNCS Sync Processor I/O Control $0045 Register Write: (SPIOCR) Reset: 0 0 U = Unaffected X = Indeterminate
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 51
Memory Map
Addr. $0046
Register Name Read: Sync Processor Control Register 1 Write: (SPCR1) Reset: USB Embedded Device Read: Control Register 2 Write: (DCR2) Reset:
Bit 7 LVSIE 0 0 0
6 LVSIF 0 0 0 0 DADD6 0 RXD0F 0 0 0 DSTALL0 0 ENDADD 0 DSETUP 0 0 0 KBIE6 0
5 HPS1 0 0 0 DADD5 0 0 0 0 0 TX0E 0 TX1E 0 DTX1ST 0 0 0 KBIE5 0
4 HPS0 0 0 0 DADD4 0 0 0 0 0 RX0E 0 0 0 0 DTX1STR 0 0 0 KBIE4 0
3 R
2 R
1 ATPOL 0
Bit 0 FSHF 0
$0047
ENABLE2 ENABLE1 DSTALL2 DSTALL1 0 DADD3 0 TXD0IE 0 TXD1IE 0 TP0SIZ3 0 TP1SIZ3 0 RP0SIZ3 0 KEYF 0 KBIE3 0 0 DADD2 0 RXD0IE 0 0 0 TP0SIZ2 0 TP1SIZ2 0 RP0SIZ2 0 0 ACKK 0 KBIE2 0 R 0 DADD1 0 0 TXD0FR 0 0 TXD1FR 0 TP0SIZ1 0 TP1SIZ1 0 RP0SIZ1 0 IMASKK 0 KBIE1 0 = Reserved 0 TP0SIZ0 0 TP1SIZ0 0 RP0SIZ0 0 MODEK 0 KBIE0 0 0 DADD0 0 0 RXD0FR 0 0
$0048
USB Embedded Device Read: DEVEN Address Register Write: (DADDR) Reset: 0 USB Embedded Device Read: TXD0F Interrupt Register 0 Write: (DIR0) Reset: 0 USB Embedded Device Read: TXD1F Interrupt Register 1 Write: (DIR1) Reset: 0 USB Embedded Device Read: T0SEQ Control Register 0 Write: (DCR0) Reset: 0 USB Embedded Device Read: T1SEQ Control Register 1 Write: (DCR1) Reset: 0 Read: DRSEQ USB Embedded Device Status Register Write: (DSR) Reset: 0 Read: Keyboard Status and Control Register Write: (KBSCR) Reset: 0 0 KBIE7 0
$0049
$004A
$004B
$004C
$004D
$004E
Read: Keyboard Interrupt Enable $004F Register Write: (KBIER) Reset: U = Unaffected
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 15)
Data Sheet 52 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $0050
Register Name Read: Unimplemented Write: Reset: Read: USB HUB Downstream Port 1 Control Register Write: (HDP1CR) Reset: USB HUB Downstream Read: Port 2 Control Register Write: (HDP2CR) Reset: USB HUB Downstream Read: Port 3 Control Register Write: (HDP3CR) Reset: USB HUB Downstream Read: Port 4 Control Register Write: (HDP4CR) Reset: Read: Unimplemented Write: Reset:
Bit 7
6
5
4
3
2
1
Bit 0
$0051
PEN1 0 PEN2 0 PEN3 0 PEN4 0
LOWSP1 0 LOWSP2 0 LOWSP3 0 LOWSP4 0
RST1 0 RST2 0 RST3 0 RST4 0
RESUM1 0 RESUM2 0 RESUM3 0 RESUM4 0
SUSP1 0 SUSP2 0 SUSP3 0 SUSP4 0
0 0 0 0 0 0 0 0
D1+ X D2+ X D3+ X D4+ X
D1- X D2- X D3- X D4- X
$0052
$0053
$0054
$0055
USB SIE Timing Interrupt Read: $0056 Register Write: (SIETIR) Reset: $0057 Read: USB SIE Timing Status Register Write: (SIETSR) Reset:
SOFF 0 RSTF 0*
EOF2F 0 0 RSTFR 0 ADD6 0 RXDF 0
EOPF 0 LOCKF 0 ADD5 0 0 0
TRANF 0 0 LOCKFR 0 ADD4 0 0 0
SOFIE 0 0 SOFFR 0 ADD3 0
EOF2IE 0 0 EOF2FR 0 ADD2 0
EOPIE 0 0 EOPFR 0 ADD1 0 0 TXDFR 0 = Reserved
TRANIE 0 0 TRANFR 0 ADD0 0 0 RXDFR 0
$0058
Read: USB HUB Address USBEN Register Write: (HADDR) Reset: 0* USB HUB Interrupt Read: Register 0 Write: (HIR0) Reset: U = Unaffected TXDF 0
* RSTF and USBEN are reset by a power-on reset (POR) only. $0059 TXDIE 0 RXDIE 0 R
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map Data Sheet 53
Memory Map
Addr. $005A
Register Name Read: Unimplemented Reset: Reset: Read: USB HUB Control Register 0 Write: (HCR0) Reset:
Bit 7
6
5
4
3
2
1
Bit 0
$005B
TSEQ 0
STALL0 0 PNEW 0 SETUP X 0 0
TXE 0 PCHG5 0 TX1ST X 0 0
RXE 0 PCHG4 0 0 TX1STR 0
TPSIZ3 0 PCHG3 0 RPSIZ3 X
TPSIZ2 0 PCHG2 0 RPSIZ2 X 0 0
TPSIZ1 0 PCHG1 0 RPSIZ1 X D0+ X
TPSIZ0 0 PCHG0 0 RPSIZ0 X D0- X
Read: USB HUB Endpoint 1 STALL1 $005C Control and Data Register Write: (HCDR) Reset: 0 Read: USB HUB Status Register $005D Write: (HSR) Reset: $005E USB HUB Root Port Read: Control Register Write: (HRPCR) Reset: Read: $005F Unimplemented Write: Reset: $0060 Read: OSDMEN OSD Control Register Write: (OSDCR) Reset: 0 Read: OSD Status Register Write: (OSDSR) Reset: WRDY 1 RSEQ X 0 0
RESUM0 SUSPND 0 0
R
OSDRST 0
CLKINV 0
CLKPH1 0
CLKPH0 HALFCLK OSDIEN 0 0 0 DENDIF 0
$0061
$0062
Read: OSDD7 OSD Data Register Low Write: (OSDDRL) Reset: Read: OSDD15 OSD Data Register High Write: (OSDDRH) Reset: U = Unaffected
OSDD6
OSDD5
OSDD4
OSDD3
OSDD2
OSDD1
OSDD0
Unaffected by reset OSDD14 OSDD13 OSDD12 OSDD11 OSDD10 OSDD9 OSDD8
$0063
Unaffected by reset = Unimplemented R = Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 15)
Data Sheet 54 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $0064
Register Name Read: OSD Row Address Register Write: (OSDRAR) Reset: Read: OSD Column Address Register Write: (OSDCAR) Reset:
Bit 7
6
5
4
3 ROWA3 0
2 ROWA2 0 COLA2 0 DOT10
1 ROWA1 0 COLA1 0 DOT9
Bit 0 ROWA0 0 COLA0 0 DOT8
$0065
COLA4 0 DOT14 DOT13 DOT12
COLA3 0 DOT11
$0066
Read: OSD FLASH Even DOT15 High Byte Write Buffer Write: (OSDEHBUF) Reset: Read: Unimplemented Write: Reset: Port E Control Read: Register Write: (PECR) Reset: Port D Control Read: IICDATE Register Write: (PDCR) Reset: 0
Unaffected by reset
$0067
$0068
R
USBDS4E USBDS3E USBDS2E USBDS1E 0 0 VOUTE 0 MMBR2 0 MMAD2 0 0 0 0 0 R 0 DEE 0 MMBR1 0 0 DCLKE 0 MMBR0 0
$0069
IICSCLE DDCDATE DDCSCLE HOUTE 0 0 MMBB 0 MMAD5 1 0 0 0 MMAST 0 MMAD4 0 0 0 0 MMRW 0 MMAD3 0 MMTXAK 0
$006A
Multi-Master IIC Read: MMALIF MMNAKIF Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 Read: Multi-Master IIC Address MMAD7 Register Write: (MMADR) Reset: 1 Read: Multi-Master IIC Control Register Write: (MMCR) Reset: MMEN 0 MMAD6 0 MMIEN 0 MMTXIF 0 0
$006B
MMAD1 MMEXTAD 0 0 0 0 0 0
$006C
$006D
Read: MMRXIF Multi-Master IIC 0 Status Register Write: (MMSR) Reset: 0 U = Unaffected
MMATCH MMSRW MMRXAK 0 0 1
MMTXBE MMRXBF 1 = Reserved 0
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 55
Memory Map
Addr. $006E
Register Name
Bit 7
6 MMTD6 1 MMRD6
5 MMTD5 1 MMRD5
4 MMTD4 1 MMRD4
3 MMTD3 1 MMRD3
2 MMTD2 1 MMRD2
1 MMTD1 1 MMRD1
Bit 0 MMTD0 1 MMRD0
Read: Multi-Master IIC MMTD7 Data Transmit Register Write: (MMDTR) Reset: 1 Multi-Master IIC Read: MMRD7 Data Receive Register Write: (MMDRR) Reset: 0 Read: 0PWM4 PWM0 Data Register Write: (0PWM) Reset: 0 Read: 1PWM4 PWM1 Data Register Write: (1PWM) Reset: 0 Read: 2PWM4 PWM2 Data Register Write: (2PWM) Reset: 0 Read: 3PWM4 PWM3 Data Register Write: (3PWM) Reset: 0 Read: 4PWM4 PWM4 Data Register Write: (4PWM) Reset: 0 Read: 5PWM4 PWM5 Data Register Write: (5PWM) Reset: 0 Read: 6PWM4 PWM6 Data Register Write: (6PWM) Reset: 0 Read: 7PWM4 PWM7 Data Register Write: (7PWM) Reset: 0 U = Unaffected
$006F
0 0PWM3 0 1PWM3 0 2PWM3 0 3PWM3 0 4PWM3 0 5PWM3 0 6PWM3 0 7PWM3 0
0 0PWM2 0 1PWM2 0 2PWM2 0 3PWM2 0 4PWM2 0 5PWM2 0 6PWM2 0 7PWM2 0
0 0PWM1 0 1PWM1 0 2PWM1 0 3PWM1 0 4PWM1 0 5PWM1 0 6PWM1 0 7PWM1 0
0 0PWM0 0 1PWM0 0 2PWM0 0 3PWM0 0 4PWM0 0 5PWM0 0 6PWM0 0 7PWM0 0
0 0BRM2 0 1BRM2 0 2BRM2 0 3BRM2 0 4BRM2 0 5BRM2 0 6BRM2 0 7BRM2 0 R
0 0BRM1 0 1BRM1 0 2BRM1 0 3BRM1 0 4BRM1 0 5BRM1 0 6BRM1 0 7BRM1 0 = Reserved
0 0BRM0 0 1BRM0 0 2BRM0 0 3BRM0 0 4BRM0 0 5BRM0 0 6BRM0 0 7BRM0 0
$0070
$0071
$0072
$0073
$0074
$0075
$0076
$0077
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 15)
Data Sheet 56 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $0078
Register Name
Bit 7
6 PWM6E 0
5 PWM5E 0
4 PWM4E 0
3 PWM3E 0
2 PWM2E 0
1 PWM1E 0
Bit 0 PWM0E 0
Read: PWM7E PWM Control Register Write: (PWMCR) Reset: 0 Read: Unimplemented Write: Reset: Read:
$0079
$007A
Unimplemented Write: Reset: Read:
$007B
Unimplemented Write: Reset: Read:
$007C
Unimplemented Write: Reset: Read:
$007D
Unimplemented Write: Reset: Read:
$007E
Unimplemented Write: Reset: Read:
$007F
Unimplemented Write: Reset:
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. U = Unaffected
R
R
R
R
R
R
SBSW Note 0
R
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 13 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 57
Memory Map
Addr.
Register Name
Bit 7 POR 1 R
6 PIN 0 R
5 COP 0 R
4 ILOP 0 R
3 ILAD 0 R
2 USB 0 R
1 0 0 R
Bit 0 0 0 R
Read: SIM Reset Status Register Write: $FE01 (SRSR) POR: Read: $FE02 Reserved Write: Reset: $FE03 SIM Break Flag Control Read: Register Write: (SBFCR) Reset:
BCFE 0 IF6 R 0 IF14 R 0 R
R
R
R
R
R
R
R
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: $FE06 Reserved Write: Reset: $FE07 47,616 Bytes FLASH Read: Control Register Write: (FLCR) Reset: Read: 47,616 Bytes FLASH Block Protect Register Write: (FLBPR) Reset: Read: $FE09 Reserved Write: Reset: $FE0A Read: 13K-Bytes FLASH Control Register Write: (FLCR1) Reset: U = Unaffected
IF5 R 0 IF13 R 0 R
IF4 R 0 IF12 R 0 R
IF3 R 0 IF11 R 0 R
IF2 R 0 IF10 R 0 R
IF1 R 0 IF9 R 0 R
0 R 0 IF8 R 0 R
0 R 0 IF7 R 0 R
0 0 BPR7 0 R
0 0 BPR6 0 R
0 0 BPR5 0 R
0 0 BPR4 0 R
HVEN 0 BPR3 0 R
MASS 0 BPR2 0 R
ERASE 0 BPR1 0 R
PGM 0 0 0 R
$FE08
0 0
0 0
0 0
0 0
HVEN1 0
MASS1 0 R
ERASE1 0 = Reserved
PGM1 0
X = Indeterminate
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 14 of 15)
Data Sheet 58 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Memory Map Input/Output (I/O) Section
Addr. $FE0B
Register Name
Bit 7
6 BPR16 0 14 0 6 0 BRKA 0
5 BPR15 0 13 0 5 0 0 0
4 BPR14 0 12 0 4 0 0 0
3 BPR13 0 11 0 3 0 0 0
2 BPR12 0 10 0 2 0 0 0
1 BPR11 0 9 0 1 0 0 0
Bit 0 0 0 Bit 8 0 Bit 0 0 0 0
Read: 13K-Bytes FLASH BPR17 Block Protect Register Write: (FLBPR1) Reset: 0 Read: Break Address High Write: Register (BRKH) Reset: Read: Break Address Low Write: Register (BRKL) Reset: Bit 15 0 Bit 7 0 BRKE 0
$FE0C
$FE0D
Break Status and Control Read: $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register Write: (COPCTL) Reset: U = Unaffected
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset X = Indeterminate = Unimplemented R = Reserved
$FFFF
Figure 2-2. Control, Status, and Data Registers (Sheet 15 of 15)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Memory Map
Data Sheet 59
Memory Map
Table 2-1. Vector Addresses
Vector Priority Lowest Vector IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector CGM PLL Interrupt Vector (High) CGM PLL Interrupt Vector (Low) Keyboard Interrupt Vector (High) Keyboard Interrupt Vector (Low) ADC Interrupt Vector (High) ADC Interrupt Vector (Low) OSD Interrupt Vector (High) OSD Interrupt Vector (Low) MMIIC Vector (High) MMIIC Vector (Low) Sync Processor Vector (High) Sync Processor Vector (Low) TIM Overflow Vector (High) TIM Overflow Vector (Low) TIM Channel 1 Vector (High) TIM Channel 1 Vector (Low) TIM Channel 0 Vector (High) TIM Channel 0 Vector (Low) DDC12AB Vector (High) DDC12AB Vector (Low) USB Device Interrupt Vector (High) USB Device Interrupt Vector (Low) USB HUB Interrupt Vector (High) USB HUB Interrupt Vector (Low) USB Vector (High) USB Vector (Low) IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
.
Highest
Data Sheet 60 Memory Map
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.2 Introduction
This section describes the 2,048 bytes of RAM (random-access memory).
3.3 Functional Description
The RAM is divided into two blocks. Addresses $0080 through $047F are locations for general use. Addresses $0800 through $0BFF are locations for the OSD display RAM (see 18.6 OSD Screen Memory Map). The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Random-Access Memory (RAM)
Data Sheet 61
Random-Access Memory (RAM)
NOTE:
For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
Data Sheet 62 Random-Access Memory (RAM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 4. FLASH Memory
4.1 Contents
4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.4 FLASH Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.1 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . . 67 4.5 4.6 4.7 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 68 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 FLASH Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . 72
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory
Data Sheet 63
FLASH Memory 4.2 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
Addr. $FE07 Register Name 47,616 Bytes FLASH Read: Control Register Write: (FLCR) Reset: 47,616 Bytes FLASH Read: Block Protect Register Write: (FLBPR) Reset: 13K-Bytes FLASH Read: Control Register Write: (FLCR1) Reset: Bit 7 0 0 BPR7 0 0 0 6 0 0 BPR6 0 0 0 BPR16 0 DOT14 5 0 0 BPR5 0 0 0 BPR15 0 DOT13 4 0 0 BPR4 0 0 0 BPR14 0 DOT12 3 HVEN 0 BPR3 0 HVEN1 0 BPR13 0 DOT11 2 MASS 0 BPR2 0 MASS1 0 BPR12 0 DOT10 1 ERASE 0 BPR1 0 ERASE1 0 BPR11 0 DOT9 Bit 0 PGM 0 0 0 PGM1 0 0 0 DOT8
$FE08
$FE0A
$FE0B
13K-Bytes FLASH Read: BPR17 Block Protect Register Write: (FLBPR1) Reset: 0 OSD FLASH Even Read: DOT15 High Byte Write Buffer Write: (OSDEHBUF) Reset:
$0066
Unaffected by reset
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The MC68HC908LD64 FLASH memory contains two arrays: * * 13,312-byte array 47,616-byte array
An additional 32 bytes of FLASH user vectors, $FFE0-$FFFF, are in the same array as the 47,616-byte. The size, address range, and memory usage of the arrays are summarized in Table 4-1.
NOTE:
Data Sheet 64
An erased bit reads as logic 1 and a programmed bit reads as logic 0.
MC68HC908LD64 -- Rev. 3.0 FLASH Memory Freescale Semiconductor
FLASH Memory Functional Description
Table 4-1. FLASH Memory Array Summary
13,312 Array Bytes Address range Minimum erase size Usage Programming Size 1,024 $0C00-$0FFF 128 bytes User data or program 12,288 $1000-$3FFF 512 bytes OSD fonts 47,616 $4000-$F9FF 512 bytes User program 47,616 Array 32 $FFE0-$FFFF 32 bytes by mass erase only User vectors
Double bytes in a 64-byte programming routine FLCR1 at $FE0A FLBPR1 at $FE0B OSDEHBUF at $0066
Single bytes in a 64-byte programming routine FLCR at $FE07 FLBPR at $FE08
Related Control registers
Each FLASH array is programmed and erased through control bits in their respective memory mapped FLASH control registers, FLCR and FLCR1. The 13K-bytes array is programmed in double bytes. Programming an odd address ($xxxx+1) location automatically programs the content in the OSD FLASH even high byte write buffer (OSDEHBUF) to the even address ($xxxx) location. Programming tools are available from Freescale. Contact your local Freescale representative for more information.
NOTE:
A security feature prevents viewing of the FLASH contents.1
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory
Data Sheet 65
FLASH Memory 4.4 FLASH Control Registers
The two FLASH control registers control FLASH program and erase operations. This register controls the 47,616-byte array:
Address: $FE07 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 HVEN MASS ERASE PGM 3 2 1 Bit 0
= Unimplemented
Figure 4-2. 47,616-byte FLASH Control Register (FLCR) This register controls the 13K-byte array:
Address: $FE0A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 HVEN1 MASS1 ERASE1 PGM1 3 2 1 Bit 0
= Unimplemented
Figure 4-3. 13K-byte FLASH Control Register (FLCR1) FLCR1 is used with the OSD FLASH even high byte write buffer (OSDEHBUF) in programming operations. See 4.4.1 OSD FLASH Even High Byte Write Buffer (OSDEHBUF). The following are bit definitions for FLCR and FLCR1. HVEN -- High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off
Data Sheet 66 FLASH Memory MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
FLASH Memory FLASH Control Registers
MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or block erase operation when the ERASE bit is set. 1 = Mass Erase operation selected 0 = Mass Erase operation not selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected
4.4.1 OSD FLASH Even High Byte Write Buffer (OSDEHBUF)
Address: $0066 Bit 7 Read: DOT15 Write: Reset: Unaffected by reset DOT14 DOT13 DOT12 DOT11 DOT10 DOT9 DOT8 6 5 4 3 2 1 0
Figure 4-4. OSD FLASH Even High Byte Write Buffer (OSDEHBUF) DOT[15:8] -- OSD FLASH Even High Byte Buffer These bits define the byte to be programmed to an even address location of the 13K-bytes array. The contents of this register will be automatically programmed to the even address ($xxxx) location when the odd address ($xxxx+1) is programmed. Reset has no effect on these bits. See 18.5 OSD FLASH Font Memory Map for OSD font memory map.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory Data Sheet 67
FLASH Memory 4.5 FLASH Block Erase Operation
The minimum erase size for the FLASH memory is one block, and is carried out by the block erase operation. For memory $0C00-$0FFF, a block consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. For memory $1000-$3FFF and $4000-$F9FF, a block consists of 512 consecutive bytes starting from addresses $x000, $x200, $x400, $x600, $x800, $xA00, $xC00, or $xE00.
NOTE:
The 32-byte user vectors, $FFE0-$FFFF, cannot be erased by the block erase operation because of security reasons. Mass erase is required to erase this block. Use the following procedure to erase a block of FLASH memory: 1. Set the ERASE bit, and clear the MASS bit in the FLASH control register. 2. Write any data to any FLASH address within the block address range desired. 3. Wait for a time, tnvs (min. 5s) 4. Set the HVEN bit. 5. Wait for a time, tErase (min. 10ms) 6. Clear the ERASE bit. 7. Wait for a time, tnvh (min. 5s) 8. Clear the HVEN bit. 9. After a time, trcv (min. 1s), the memory can be accessed again in read mode.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the same FLASH array that is being programmed or erased. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
Data Sheet 68 FLASH Memory
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
FLASH Memory FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
A mass erase operation erases an entire array of FLASH memory. The MC68HC908LD64 contains two FLASH memory arrays, therefore, two mass erase operations are required to erase all FLASH memory in the device. Mass erasing the 13K-byte array, erases all FLASH memory from $0800 to $3FFF. Mass erasing the 47,616-byte array, erases all FLASH memory from $4000 to $FFFF. Use the following procedure to erase an entire FLASH memory array: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Write any data to any FLASH address within the FLASH memory address range. 3. Wait for a time, tnvs (5s). 4. Set the HVEN bit. 5. Wait for a time, tERASE (10ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvhl (100s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed again in read mode.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the same FLASH array that is being programmed or erased. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory
Data Sheet 69
FLASH Memory 4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, and $XXC0. Use this step-by-step procedure to program a row of FLASH memory (Figure 4-5 is a flowchart representation):
NOTE:
In order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH address within the row address range desired. 3. Wait for a time, tnvs (min. 5s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (min. 10s). 6. For 47,616-byte array: Write data to the FLASH address to be programmed. For 13K-byte array: Write even address data to OSDEHBUF then write odd address data to the odd FLASH address to be programmed. 7. Wait for time, tPROG (min. 20s). 8. Repeat step 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (min. 5s). 11. Clear the HVEN bit. 12. After time, trcv (min 1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the same FLASH array that is being programmed or erased. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum. See 24.14 FLASH Memory Characteristics.
MC68HC908LD64 -- Rev. 3.0 FLASH Memory Freescale Semiconductor
Data Sheet 70
FLASH Memory FLASH Program Operation
1
Set PGM bit
Algorithm for programming a row (64 bytes) of FLASH memory
2
Write any data to any FLASH address within the row address range desired
3
Wait for a time, tnvs
4
Set HVEN bit
5
Wait for a time, tpgs
6 For 47,616 bytes array
For 13K-bytes array
Write even byte to OSD FLASH Even High Byte Write Buffer at $0066. Write odd byte to the FLASH address to be programmed.
Write data to the FLASH address to be programmed
7
Wait for a time, tprog
Completed programming this row? N
9
Y
NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
End of Programming
Figure 4-5. FLASH Programming Flowchart
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory Data Sheet 71
FLASH Memory 4.8 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH Block Protect Register for each array (FLBPR and FLBPR1). The block protect register determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by block protect register and ends at the bottom of the FLASH memory array ($FFFF and $3FFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.
4.8.1 FLASH Block Protect Registers Each FLASH block protect register is implemented as an 7-bit I/O register. The BPR bit content of the register determines the starting location of the protected range within the FLASH memory. This register controls the 47,616-byte array:
Address: $FE08 Bit 7 Read: BPR7 Write: Reset: 0 0 0 0 0 0 0 0 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 6 5 4 3 2 1 Bit 0 0
Figure 4-6. 47,616-byte FLASH Block Protect Register (FLBPR) This register controls the 13K-byte array:
Address: $FE0B Bit 7 Read: BPR17 Write: Reset: 0 0 0 0 0 0 0 0 BPR16 BPR15 BPR14 BPR13 BPR12 BPR11 6 5 4 3 2 1 Bit 0 0
Figure 4-7. 13K-byte FLASH Block Protect Register 1 (FLBPR1)
Data Sheet 72 FLASH Memory
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
FLASH Memory FLASH Block Protection
BPR[7:1] -- FLASH Block Protect Bits These seven bits represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. BPR1[7:1] -- FLASH Block Protect Bits These seven bits represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $3FFF.
16-bit memory address Start address of FLASH block protect BPR[7:1] 000000000 0
Figure 4-8. FLASH Block Protect Start Address Examples of block protection for 47,616-byte FLASH memory array:
BPR[7:0] $40 $42 (0100 0010) $44 (0100 0100) and so on... $F8 (1111 1000) $FA $FC $FE $00-3E $F800 (1111 1000 0000 0000) to $FFFF $FFE0 to $FFFF (FLASH Vectors) $FFE0 to $FFFF (FLASH Vectors) $FFE0 to $FFFF (FLASH Vectors) The entire 47,616 bytes FLASH memory is not protected. FLASH Memory Protected Range The entire 47,616 bytes of FLASH memory is protected. $4200 (0100 0010 0000 0000) to $FFFF $4400 (0100 0100 0000 0000) to $FFFF
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor FLASH Memory
Data Sheet 73
FLASH Memory
Examples of block protection for 13K-byte FLASH memory array:
BPR1[7:0] $0C $0E (0000 1110) $10 (0001 0000) and so on... $38 (0011 1000) $3A (0011 1010) $3C (0011 1100) $3E (0011 1110) $00-$0B or $40-$FE $3800 (0011 1000 0000 0000) to $3FFF $3A00 (0011 1010 0000 0000) to $3FFF $3C00 (0011 1100 0000 0000) to $3FFF $3E00 (0011 1110 0000 0000) to $3FFF The entire 13K-byte FLASH memory is not protected. FLASH Memory Protected Range The entire 13K-byte FLASH memory is protected. $0E00 (0000 1110 0000 0000) to $3FFF $1000 (0001 0000 0000 0000) to $3FFF
Data Sheet 74 FLASH Memory
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.2 Introduction
This section describes the configuration register, CONFIG. The configuration register enables or disables these options: * * * * Stop mode recovery time (32 OSCXCLK cycles or 4096 OSCXCLK cycles) COP timeout period (218 - 24 or 213 - 24 OSCXCLK cycles) STOP instruction Computer operating properly module (COP)
5.3 Functional Description
The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Configuration Register (CONFIG)
Data Sheet 75
Configuration Register (CONFIG) 5.4 Configuration Register
Address: $001F Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 SSREC COPRS STOP COPD 3 2 1 Bit 0
= Unimplemented
Figure 5-1. Configuration Register (CONFIG) SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 OSCXCLK cycles instead of a 4096 OSCXCLK cycle delay. 1 = Stop mode recovery after 32 OSCXCLK cycles 0 = Stop mode recovery after 4096 OSCXCLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit. COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. (See Section 22. Computer Operating Properly (COP).) 1 = COP timeout period = 213 - 24 OSCXCLK cycles 0 = COP timeout period = 218 - 24 OSCXCLK cycles STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 22. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
Data Sheet 76 Configuration Register (CONFIG)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 77
Central Processor Unit (CPU) 6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
6.3 Features
Feature of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-Bit index register with X-register manipulation instructions 6-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes Low-power stop and wait modes
Data Sheet 78 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) CPU Registers
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
7 0 V11HINZC
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7
Read: Write: Reset: Unaffected by reset
6
5
4
3
2
1
Bit 0
Figure 6-2. Accumulator (A)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 79
Central Processor Unit (CPU)
6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-4. Stack Pointer (SP)
Data Sheet 80 Central Processor Unit (CPU) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) CPU Registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15
Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-5. Program Counter (PC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 81
Central Processor Unit (CPU)
6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7
Read:
6 1 1
5 1 1
4 H X
3 I 1
2 N X
1 Z X
Bit 0 C X
V
Write: Reset:
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4
Data Sheet 82 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) CPU Registers
I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 83
Central Processor Unit (CPU)
C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock.
*
Data Sheet 84 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) CPU During Break Interrupts
6.6.2 Stop Mode The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock.
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. (See Section 23. Break Module (BRK).) The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 85
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operand ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd Address Mode Opcode A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F Effect on CCR VHINZC
Operation
Description
Add with Carry
A (A) + (M) + (C)
-
IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn 0
Data Sheet 86 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 2 of 8)
Cycles 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 Source Form BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operand rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr Address Mode Opcode 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 Effect on CCR VHINZC Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
Operation
Description
- - - - - - REL - - - - - - REL - - - - - - REL
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL
PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 - IX1 IX SP1 SP2
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 87
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Cycles 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 dd 3 1 1 1 3 2 4 Source Form Operand dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr ff ff Address Mode Opcode 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F Effect on CCR VHINZC
Operation
Description
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRN rel
Branch Never
PC (PC) + 2
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
-----
BSET n,opr
Set Bit n in M
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel
- - - - - - REL
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask
DIR PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (X) - (M) = $00 ------ IX1+ PC (PC) + 3 + rel ? (A) - (M) = $00 IX+ PC (PC) + 2 + rel ? (A) - (M) = $00 SP1 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
Clear
Data Sheet 88 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 dd rr rr rr ff rr rr ff rr dd 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Operand ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff ff ff Address Mode Opcode A1 B1 C1 D1 E1 F1 9EE1 9ED1 33 43 53 63 73 9E63 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Effect on CCR VHINZC
Operation
Description
Compare A with M
(A) - (M)
--
IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
Compare H:X with M
--
Compare X with M
(X) - (M)
--
Decimal Adjust A
(A)10
A (A) - 1 or M (M) - 1 or X (X) - 1
U--
DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder
DIR INH - - - - - - INH IX1 IX SP1 DIR INH INH - IX1 IX SP1 INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Decrement
--
Divide
----
Exclusive OR M with A
A (A M)
0--
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 89
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 8)
Cycles 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 Source Form INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Operand dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff Address Mode Opcode 3C 4C 5C 6C 7C 9E6C BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE 38 48 58 68 78 9E68 34 44 54 64 74 9E64 Effect on CCR VHINZC M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
Operation
Description
Increment
--
DIR INH INH - IX1 IX SP1
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2 - IMM DIR
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Load H:X from M
H:X (M:M + 1)
0--
Load X from M
X (M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
--
Logical Shift Right
0 b7 b0
C
--0
Data Sheet 90 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Cycles 5 4 4 4 5 dd 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 dd 4 1 1 4 3 5 4 1 1 4 3 5 1 Source Form MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operand dd dd dd ii dd dd ff ff ff ff dd ff ff Address Mode Opcode 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 49 59 69 79 9E69 36 46 56 66 76 9E66 9C Effect on CCR VHINZC (M)Destination (M)Source Move H:X (H:X) + 1 (IX+D, DIX+) Unsigned multiply X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4]) 0--
Operation
Description
DD DIX+ - IMD IX+D
- 0 - - - 0 INH DIR INH INH IX1 IX SP1
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Rotate Left through Carry
C b7 b0
--
Rotate Right through Carry
b7 b0
C
--
Reset Stack Pointer
SP $FF
- - - - - - INH
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 91
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Cycles 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 Source Form Operand Address Mode Opcode 80 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 Effect on CCR VHINZC SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
Operation
Description
RTI
Return from Interrupt
INH
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
Data Sheet 92 Central Processor Unit (CPU)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Cycles 9 2 1 1 dd 3 1 1 3 2 4 2 1 2 Source Form Operand ff ff Address Mode Opcode 83 84 97 85 3D 4D 5D 6D 7D 9E6D 95 9F 94 Effect on CCR VHINZC PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
Operation
Description
SWI
Software Interrupt
- - 1 - - - INH
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1 n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) # ? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Central Processor Unit (CPU)
Data Sheet 93
94 Central Processor Unit (CPU) Freescale Semiconductor
Data Sheet
LSB
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Bit Manipulation DIR DIR
MSB
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
DIR 3
INH 4
Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
SP1 9E6
IX 7
Control INH INH 8 9
IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM
DIR B
EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT
Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2
IX1 E
SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1
IX F
0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4 5 6 7 8 9 A B C D E F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908LD64 -- Rev. 3.0
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Data Sheet -- MC68HC908LD64
Section 7. Oscillator (OSC)
7.1 Contents
7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .96
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 97 7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 97 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 97 7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 97 7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.2 Introduction
The oscillator circuit is designed for use with crystals or ceramic resonators. The oscillator circuit generates the crystal clock signal, OSCXCLK, at the frequency of the crystal. This signal is divided by two before being passed on to the SIM for bus clock generation. Figure 7-1 shows the structure of the oscillator. The oscillator requires various external components. The MC68HC908LD64 operates from a nominal 24MHz crystal or external clock, providing an 8MHz internal bus clock. The 24MHz clock is required for various modules, such as the CGM and USB.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Oscillator (OSC)
Data Sheet 95
Oscillator (OSC) 7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external components. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 (nominally 24MHz) Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (not required for 24MHz crystal)
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information.
From SIM To SIM To SIM
OSCXCLK SIMOSCEN
/2
OSCOUT
MCU OSC1 OSC2 RS * RB *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data.
X1
C1
24MHz
C2
Figure 7-1. Oscillator External Connections
Data Sheet 96 Oscillator (OSC) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Oscillator (OSC) I/O Signals
7.4 I/O Signals
The following paragraphs describe the oscillator I/O signals.
7.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
7.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the SIM and enables the oscillator.
7.4.4 External Clock Source (OSCXCLK) OSCXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 7-1 shows only the logical relation of OSCXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of OSCXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of OSCXCLK can be unstable at start-up.
7.4.5 Oscillator Out (OSCOUT) The clock driven to the SIM is the crystal frequency divided by two. This signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the OSCXCLK frequency.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Oscillator (OSC) Data Sheet 97
Oscillator (OSC) 7.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCXCLK continues to drive to the SIM module.
7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues drive OSCXCLK when the chip enters the break state.
Data Sheet 98 Oscillator (OSC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 8. Clock Generator Module (CGM)
8.1 Contents
8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.5 CGM I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 103 8.5.2 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 103 8.5.3 PLL Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 103 8.5.4 Crystal Output Frequency Signal (OSCXCLK). . . . . . . . . . 104 8.5.5 Crystal Reference Frequency Signal (OSCRCLK). . . . . . . 104 8.5.6 CGM Base Clock Output (DCLK1) . . . . . . . . . . . . . . . . . . . 104 8.5.7 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 104 8.6 CGM I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 106 8.6.3 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . 108 8.6.4 H & V Sync Output Control Register (HVOCR) . . . . . . . . . 110 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 112
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 99
Clock Generator Module (CGM) 8.2 Introduction
This section describes the clock generator module (CGM). Using the crystal reference clock from the oscillator module, the CGM generates the display base clock, DCLK1, for the sync processor module. The CGM is able to generate a frequency up to 108MHz from a 24MHz reference clock.
8.3 Features
Features of the CGM include the following: * * * * * Phase-locked loop with output frequency in integer multiples of the crystal reference Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition
8.4 Functional Description
The CGM consists of three major sub-modules: * Crystal oscillator circuit which generates the buffered constant crystal frequency clock, OSCRCLK. (See Section 7. Oscillator (OSC).) Phase-locked loop (PLL) which generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit; this software-controlled circuit selects either OSCXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock DCLK1. The sync processor derives other display clocks from DCLK1.
* *
Data Sheet 100 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM) Functional Description
OSCILLATOR (OSC) (See Section 7. Oscillator (OSC).) OSC2 OSCOUT /2 OSC1 OSCXCLK (TO SIM) SIMOSCEN (FROM SIM)
PHASE-LOCKED LOOP (PLL) HVOCR[1:0]
CGMRDV
REFERENCE DIVIDER
OSCRCLK BCS CLOCK SELECT CIRCUIT DCLK1 (TO SYNC PROCESSOR)
VDDA
CGMXFC
VSSA
VRS[7:4] L
PHASE DETECTOR
LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR PLL ANALOG
LOCK DETECTOR
BANDWIDTH CONTROL
INTERRUPT CONTROL
CGMINT (TO SIM)
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[7:4] N CGMVDV FREQUENCY DIVIDER CGMVCLK
Figure 8-1. CGM Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 101
Clock Generator Module (CGM)
Addr. $0038
Register Name Read: PLL Control Register Write: (PCTL) Reset: PLL Bandwidth Control Read: Register Write: (PBWC) Reset: PLL Programming Read: Register Write: (PPG) Reset:
Bit 7 PLLIE 0 AUTO 0 MUL7 0
6 PLLF 0 LOCK 0 MUL6 1
5 PLLON 1 ACQ 0 MUL5 1
4 BCS 0 XLD 0 MUL4 0
3 1 1 0 0 VRS7 0
2 1 1 0 0 VRS6 1 R
1 1 1 0 0 VRS5 1
Bit 0 1 1 0 0 VRS4 0
$0039
$003A
H&V Sync Output Control Read: $003F Register Write: (HVOCR) Reset: = Unimplemented
NOTES: 1. When AUTO = 0, PLLIE is forced to logic zero and is read-only. 2. When AUTO = 0, PLLF and LOCK read as logic zero. 3. When AUTO = 1, ACQ is read-only.
DCLKPH1 DCLKPH0 0 0 R
HVOCR1 HVOCR0 0 0
= Reserved
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-2. CGM I/O Register Summary
Table 8-1. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
Register Settings HVOCR[1:0] 00 01 10 11 MUL[7:4] 3 5 8 9 VRS[7:4] 3 3 6 9 HOUT Frequency 31.45kHz 37.87kHz 48.37kHz 64.32kHz Output Pin VOUT Frequency 59.91Hz 60.31Hz 60.31Hz 60.00Hz DCLK Frequency 24MHz 40MHz 64MHz 108MHz Video Modes DE Video Mode VGA 640 x 480 SVGA 800 x 600 XGA 1024 x 768 SXGA 1280 x 1024
Data Sheet 102 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM) CGM I/O Signals
8.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit. The OSCXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. OSCXCLK is then buffered to produce OSCRCLK, the PLL reference clock. (See Section 7. Oscillator (OSC).)
8.5 CGM I/O Signals
The following paragraphs describe the CGM I/O signals.
8.5.1 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor (CF) is connected to this pin.
NOTE:
To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the CF connection.
8.5.2 PLL Analog Power Pin (VDDA) VDDA is the power pin used by the analog portions of the PLL. The pin should be connected to the same voltage potential as the VDD pin.
8.5.3 PLL Analog Ground Pin (VSSA) VSSA is the ground pin used by the analog portions of the PLL. The pin should be connected to the same voltage potential as the VSS pin.
NOTE:
Route VDDA and VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 103
Clock Generator Module (CGM)
8.5.4 Crystal Output Frequency Signal (OSCXCLK) OSCXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and is generated directly from the crystal oscillator circuit. The duty cycle of OSCXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of OSCXCLK can be unstable at start-up.
8.5.5 Crystal Reference Frequency Signal (OSCRCLK) OSCRCLK is the buffered version of OSCXCLK. It runs at the full speed of the crystal (fXCLK) and provides the reference for the PLL circuit.
8.5.6 CGM Base Clock Output (DCLK1) DCLK1 is the clock output of the CGM. This signal goes to the sync processor, which generates the display clocks. DCLK1 is software programmable to be either the oscillator output (OSCXCLK) or the VCO clock (CGMVCLK).
8.5.7 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector.
8.6 CGM I/O Registers
The following registers control and monitor operation of the CGM: * * * * PLL control register (PCTL) PLL bandwidth control register (PBWC) PLL programming register (PPG) H & V sync output control register (HVOCR)
Data Sheet 104 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM) CGM I/O Registers
8.6.1 PLL Control Register (PCTL) The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit.
Address: $0038 Bit 7 Read: PLLIE Write: Reset: 0 0 1 0 1 1 1 1 6 PLLF PLLON BCS 5 4 3 1 2 1 1 1 Bit 0 1
= Unimplemented
Figure 8-3. PLL Control Register (PCTL) PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF -- PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit is set also. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. The PLLF bit should be cleared by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition
NOTE:
The PLLF bit should not be inadvertently cleared. Any read or readmodify-write operation on the PLL control register clears the PLLF bit.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 105
Clock Generator Module (CGM)
PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, DCLK1 (BCS = 1). Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base Clock Select Bit This read/write bit selects either the crystal oscillator output, OSCXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, DCLK1. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three OSCXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, DCLK1 is held in stasis. Reset and the STOP instruction clear the BCS bit. 1 = DCLK1 driven by CGMVCLK 0 = DCLK1 driven by OSCXCLK
NOTE:
PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register.
8.6.2 PLL Bandwidth Control Register (PBWC) The PLL bandwidth control register does the following: * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode
MC68HC908LD64 -- Rev. 3.0 Clock Generator Module (CGM) Freescale Semiconductor
Data Sheet 106
Clock Generator Module (CGM) CGM I/O Registers
Address:
$0039 Bit 7 6 LOCK AUTO ACQ 0 0 XLD 0 0 0 0 0 5 4 3 0 2 0 1 0 Bit 0 0
Read: Write: Reset: 0
= Unimplemented
Figure 8-4. PLL Bandwidth Control Register (PBWC) AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), the ACQ bit should be cleared before turning the PLL on. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 107
Clock Generator Module (CGM)
XLD -- Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving DCLK1, this read/write bit indicates whether the crystal reference frequency is active or not. To check the status of the crystal reference, the following procedure should be followed: 1. Write a 1 to XLD. 2. Wait 4 x N cycles. (N is the VCO frequency multiplier, MUL[7:4].) 3. Read XLD. 1 = Crystal reference is not active 0 = Crystal reference is active The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive DCLK1. When BCS is clear, XLD always reads as 0. Bits [3:0] -- Reserved for test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write zeros to Bits [3:0] whenever writing to PBWC. 8.6.3 PLL Programming Register (PPG) The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO.
Address: $003A Bit 7 Read: MUL7 Write: Reset: 0 1 1 0 0 1 1 0 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 6 5 4 3 2 1 Bit 0
Figure 8-5. PLL Programming Register (PPG)
Data Sheet 108 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM) CGM I/O Registers
MUL[7:4] -- Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6. Table 8-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 VCO Frequency Multiplier (N) 1 1 2 3
1101 1110 1111
13 14 15
NOTE:
The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS[7:4] -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency fVRS. VRS[7:4] cannot be written when the PLLON bit in the PLL control register (PCTL) is set. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. Reset initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock.
Data Sheet Clock Generator Module (CGM) 109
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM)
8.6.4 H & V Sync Output Control Register (HVOCR) The H&V sync output control register controls the PLL reference input prescaler and the final free-running waveforms for the sync processor output signals on HOUT, VOUT, DCLK, and DE pins. (See Section 17. Sync Processor.)
Address: $003F Bit 7 Read: DCLKPH1 DCLKPH0 Write: Reset: = Unimplemented 0 0 R = Reserved 0 0 R HVOCR1 HVOCR0 6 5 4 3 2 1 Bit 0
Figure 8-6. H&V Sync Output Control Register (HVOCR) DCLKPH[1:0] -- DCLK Output Phase Adjustment These two bits are programmed to adjust the DCLK output phase. Each increment adds approximately 2 to 3ns delay to the DCLK output. HVOCR[1:0] -- Free Running Video Mode Select Bits These two bits together with MUL[7:4] and VRS[7:4] in the PLL programming register determine the frequencies of the internal generated free-running signals for output to HOUT, VOUT, DE, and DCLK pins, when the SOUT bit is set in the sync processor I/O control register. These two bits determine the prescaler of PLL reference clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2; for other values, the prescaler is 3. Reset clears these bits, setting a default horizontal frequency of 31.25kHz and a vertical frequency of 60Hz, a video mode of 640x480.
Register Settings HVOCR[1:0] 00 01 10 11 MUL[7:4] 3 5 8 9 VRS[7:4] 3 3 6 9 HOUT Frequency 31.45kHz 37.87kHz 48.37kHz 64.32kHz Pin Outputs VOUT Frequency 59.91Hz 60.31Hz 60.31Hz 60.00Hz DCLK Frequency 24MHz 40MHz 64MHz 108MHz Video Modes DE Video Mode VGA 640 x 480 SVGA 800 x 600 XGA 1024 x 768 SXGA 1280 x 1024
Data Sheet 110 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Clock Generator Module (CGM) Interrupts
8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock CGMVCLK, can be selected as the DCLK1 source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency-sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. Software can select CGMVCLK as the DCLK1 source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
8.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
8.8.1 Wait Mode The WAIT instruction does not affect the CGM. Before entering WAIT mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Clock Generator Module (CGM)
Data Sheet 111
Clock Generator Module (CGM)
8.8.2 Stop Mode When the STOP instruction executes, the SIM drives the SIMOSCEN signal low, disabling the CGM and holding low all CGM outputs (OSCXCLK, DCLK1, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, driving DCLK1, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, OSCXCLK, as the source of DCLK1. When the MCU recovers from STOP, the crystal clock drives DCLK1 and BCS remains clear.
8.9 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See Section 9. System Integration Module (SIM). To allow software to clear status bits during a break interrupt, a 1 should be written to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
Data Sheet 112 Clock Generator Module (CGM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 9. System Integration Module (SIM)
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 117 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 117 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 119 9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 121 9.4.2.3 Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . .121 9.4.2.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.2.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 122 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 122 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 123 9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 130
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 113
System Integration Module (SIM)
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 134 9.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 135 9.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 136
9.2 Introduction
This section describes the system integration module, which supports up to 16 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 9-1. Figure 9-2 shows a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
Data Sheet 114 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
OSCXCLK (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) /2
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) LVI RESET RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 9-1. SIM Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 115
System Integration Module (SIM)
Addr.
Register Name
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW Note 0
Bit 0 R
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Reset Status Register $FE01 Write: (SRSR) POR: Read: SIM Break Flag Control Register Write: (SBFCR) Reset:
POR
PIN
COP
ILOP
ILAD
USB
0
0
1 BCFE 0 IF6 R 0 IF14 R 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
$FE03
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 (INT2) Write: Reset:
Note: Writing a logic 0 clears SBSW.
IF5 R 0 IF13 R 0
IF4 R 0 IF12 R 0
IF3 R 0 IF11 R 0
IF2 R 0 IF10 R 0 R
IF1 R 0 IF9 R 0 = Reserved
0 R 0 IF8 R 0
0 R 0 IF7 R 0
= Unimplemented
Figure 9-2. SIM I/O Register Summary Table 9-1 shows the internal signal names used in this section. Table 9-1. Signal Name Conventions
Signal Name OSCXCLK OSCOUT IAB IDB PORRST IRST R/W Description Buffered version of OSC1 from the oscillator The OSCXCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = OSCXCLK divided by four) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
Data Sheet 116 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) SIM Bus Clock Control and Generation
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 9-3.
From SIM
OSCXCLK OSCOUT
SIM COUNTER /2 BUS CLOCK GENERATORS
/2 SIMOSCEN
OSCILLATOR OSC1 OSC2
SIM
Figure 9-3. OSC Clock Signals
9.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (OSCXCLK) divided by four.
9.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 OSCXCLK cycle POR timeout has completed. The RST is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
9.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode (by an interrupt, break, or reset), the SIM allows OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 OSCXCLK cycles. (See 9.7.2 Stop Mode.)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 117
System Integration Module (SIM)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
9.4 Reset and System Initialization
The MCU has the following reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit (LVI) Illegal opcode Illegal address
All of these resets produce the vector $FFFE-$FFFF ($FEFE-$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 9.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR) (see 9.8 SIM Registers). 9.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 OSCXCLK cycles, assuming that the POR was not the source of the reset (see Table 9-2. PIN Bit Set Timing). Figure 9-4 shows the relative timing. Table 9-2. PIN Bit Set Timing
Reset Type POR All others Data Sheet 118 System Integration Module (SIM) Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Reset and System Initialization
OSCOUT
RST
IAB
PC
VECT H VECT L
Figure 9-4. External Reset Timing 9.4.2 Active Resets from Internal Sources SIM module in HC08 has the capability to drive the RST pin low when internal reset events occur. All internal reset sources actively pull the RST pin low for 32 OSCXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 95. Internal Reset Timing). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, or POR (see Figure 9-6. Sources of Internal Reset). Note that for POR resets, the SIM cycles through 4096 OSCXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 9-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
OSCXCLK
IAB
VECTOR HIGH
Figure 9-5. Internal Reset Timing
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET
Figure 9-6. Sources of Internal Reset
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM) Data Sheet 119
System Integration Module (SIM)
9.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive OSCXCLK. Internal clocks to the CPU and modules are held inactive for 4096 OSCXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES OSCXCLK 32 CYCLES 32 CYCLES
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 9-7. POR Recovery
Data Sheet 120 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Reset and System Initialization
9.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 212 - 24 OSCXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST pin or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 9.4.2.3 Low-Voltage Inhibit Reset The low-voltage inhibit circuit performs an internal reset when the VDD voltage falls to the LVI trip voltage VTRIPF. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. 9.4.2.4 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the configure register (CONFIG) is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 121
System Integration Module (SIM)
9.4.2.5 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
9.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of OSCXCLK.
9.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.
9.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configure register (CONFIG). If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 OSCXCLK cycles down to 32 OSCXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared.
Data Sheet 122 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Exception Control
9.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter (see 9.7.2 Stop Mode). The SIM counter is free-running after all reset states (see 9.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences).
9.6 Exception Control
Normally, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 123
System Integration Module (SIM)
9.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 9-10 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 9-8 shows interrupt entry timing. Figure 9-9 shows interrupt recovery timing.
MODULE INTERRUPT I BIT
IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 9-8. Interrupt Entry
MODULE INTERRUPT I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[15:8] PC - 1[7:0]
OPCODE
OPERAND
R/W
Figure 9-9. Interrupt Recovery
Data Sheet 124 System Integration Module (SIM) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Exception Control
FROM RESET
BREAK INTERRUPT? I BIT SET? NO
YES
YES
I BIT SET?
NO
IRQ INTERRUPT? NO
YES
USB INTERRUPT? NO (As many interrupts as exist on chip)
YES
STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
Figure 9-10. Interrupt Processing
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 125
System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 9-10. Interrupt Processing.) 9.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 9-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 9-11. Interrupt Recognition Example
Data Sheet 126 System Integration Module (SIM) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Exception Control
The LDA opcode is pre-fetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI pre-fetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
9.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
9.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 127
System Integration Module (SIM)
Table 9-3. Interrupt Sources
Source Reset SWI Instruction IRQ pin HUB start of frame HUB 2nd end of frame point HUB end of packet HUB bus signal transition detect HUB endpoint 0 transmit HUB endpoint 0 receive Device endpoint 0 transmit Device endpoint 0 receive USB endpoint1/2 transmit Flag None None IRQF SOFF EOF2F EOPF TRANF TXDF RXDF TXD0F RXD0F TXD1F ALIF NAKIF DDC12AB RXIF TXIF SCLIF TIM channel 0 TIM channel 1 TIM overflow Sync processor CH0F CH1F TOF VSIF LVSIF MMALIF Multi-master IIC MMNAKIF MMRXIF MMTXIF On-screen display ADC conversion complete Keyboard Interrupt CGM PLL DENDIF COCO KEYF PLLF OSDIE AIEN KBIE7-KBIE0 PLLIE IF11 IF12 IF13 IF14 11 12 13 14 $FFE6-$FFE7 $FFE4-$FFE5 $FFE2-$FFE3 $FFE0-$FFE1 MMIEN IF10 10 $FFE8-$FFE9 SCLIEN CH0IE CH1IE TOIE VSIE LVSIE IF6 IF7 IF8 IF9 6 7 8 9 $FFF0-$FFF1 $FFEE-$FFEF $FFEC-$FFED $FFEA-$FFEB DIEN IF5 5 $FFF2-$FFF3 Mask(1) None None IMASK SOFIE EOF2IE EOPIE TRANIE TXDIE RXDIE TXD0IE RXD0IE TXD1IE IF4 4 $FFF4-$FFF5 IF3 3 $FFF6-$FFF7 IF2 2 $FFF8-$FFF9 INT Register Flag None None IF1 Priority(2) 0 0 1 Vector Address $FFFE-$FFFF $FFFC-$FFFD $FFFA-$FFFB
Notes: 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. Highest priority = 0.
Data Sheet 128 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Exception Control
9.6.2.1 Interrupt Status Register 1
Address: $FE04 Bit 7 Read: Write: Reset: IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 9-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 -- Always read 0 9.6.2.2 Interrupt Status Register 2
Address: $FE05 Bit 7 Read: Write: Reset: IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
Figure 9-13. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 129
System Integration Module (SIM)
9.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated.
9.6.4 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output (see Section 23. Break Module (BRK)). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
9.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
Data Sheet 130 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Low-Power Modes
9.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 9.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 9-14 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in configuration register (CONFIG) is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 9-14. Wait Mode Entry Timing Figure 9-15 and Figure 9-16 show the timing for WAIT recovery.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 131
System Integration Module (SIM)
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 9-15. Wait Recovery from Interrupt or Break
32 Cycles IAB $6E0B
32 Cycles RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
OSCXCLK
Figure 9-16. Wait Recovery from Internal Reset
9.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 OSCXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by clearing the SSREC bit.
Data Sheet 132 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) Low-Power Modes
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 9-17 shows stop mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 9-17. Stop Mode Entry Timing
STOP RECOVERY PERIOD OSCXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 9-18. Stop Mode Recovery from Interrupt or Break
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM)
Data Sheet 133
System Integration Module (SIM) 9.8 SIM Registers
The SIM has three memory mapped registers. Table 9-4 shows the mapping of these registers. Table 9-4. SIM Registers Summary
Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access Mode User User User
9.8.1 SIM Break Status Register (SBSR) The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address: $FE00 Bit 7 Read: R Write: Reset:
Note: Writing a logic 0 clears SBSW.
6 R
5 R
4 R
3 R
2 R
1 SBSW
Bit 0 R
Note 0 R = Reserved
Figure 9-19. SIM Break Status Register (SBSR) SBSW -- SIM Break Stop/Wait Bit This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example.
Data Sheet 134 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
System Integration Module (SIM) SIM Registers
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register.
9.8.2 SIM Reset Status Register (SRSR) This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address: $FE01 Bit 7 Read: Write: POR: 1 0 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 USB 1 0 Bit 0 0
= Unimplemented
Figure 9-20. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor System Integration Module (SIM) Data Sheet 135
System Integration Module (SIM)
COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR USB -- Universal Serial Bus Reset Bit 1 = Last reset caused by an USB module 0 = POR or read of SRSR
9.8.3 SIM Break Flag Control Register (SBFCR) The SIM break flag control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: BCFE Write: Reset: 0 R = Reserved R R R R R R R 6 5 4 3 2 1 Bit 0
Figure 9-21. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Data Sheet 136 System Integration Module (SIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 10. Monitor ROM (MON)
10.1 Contents
10.2 10.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Monitor ROM (MON)
Data Sheet 137
Monitor ROM (MON) 10.3 Features
Features of the monitor ROM include: * * * * * * * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in RAM or FLASH FLASH memory security feature1 FLASH memory programming interface 1024 bytes monitor ROM code size ($FA00 to $FDFF) Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage, VTST, is applied to IRQ
10.4 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Data Sheet 138 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Monitor ROM (MON) Functional Description
VDD 68HC908LD64 10 k RST VTST 10 C (See NOTES) D OSC1 20 pF X1 9.8304 MHz 10 M OSC2 1 10 F + 3 4 10 F + MC145407 20 + 18 17 + 10 F VDD VDD VDD1 0.1 F DB-25 2 3 7 VDD 1 2 6 4 VDD 7 10 k A (See NOTES) B NOTES: 1. SW2: Position C -- For monitor mode entry when IRQ = VTST: SW1: Position A -- Bus clock = OSCXCLK / 4 SW1: Position B -- Bus clock = OSCXCLK / 2 2. SW2: Position D -- For monitor mode entry when reset vector is blank ($FFFE and $FFFF = $FF): Bus clock = OSCXCLK / 4; PTC0, PTC1, and PTC3 voltages are not required. 3. See Table 24-4 for IRQ voltage level requirements. VDD 10 k PTC0 PTC1 PTA7 MC74LCX125 14 3 5 VDD 10 k PTA0 5 6 16 15 VDD 0.1 F VDDA DPLUS0 DMINUS0 PTD4/DDCSCL PTD5/DDCSDA VDD2 10 F 20 pF VSS1 VSS2 VSSA 0.1 F
SW2 IRQ
2
19
PTC3
SW1
Figure 10-1. Monitor Mode Circuit
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Monitor ROM (MON) Data Sheet 139
Monitor ROM (MON)
10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If monitor entry is by high voltage on IRQ (IRQ = VTST) - The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high 2. If monitor entry is by blank reset vector ($FFFE and $FFFF both contain $FF; erased state): - The external clock is 9.8304 MHz
NOTE:
Holding the PTC3 pin low when entering monitor mode by a high voltage causes a bypass of a divide-by-two stage at the oscillator. The OSCOUT frequency is equal to the OSCXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a high voltage, VTST, to IRQ must be used to enter monitor mode. Enter monitor mode with the pin configuration shown in Table 10-1 after a reset. The rising edge of reset latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU monitor mode firmware then sends a break signal (10 consecutive logic zeros) to the host computer, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate.
NOTE:
Data Sheet 140 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Freescale Semiconductor Monitor ROM (MON) 141
MC68HC908LD64 -- Rev. 3.0 Data Sheet
Table 10-1. Monitor Mode Signal Requirements and Options
IRQ RST Address $FFFE/ $FFFF X PTC3 PTC1 PTC0 PTA7(1) DPLUS0 DMINUS0 PTD4 PTD5 X External Clock(2) X Bus Frequency 0 COP Baud Rate 0 Comment
X
GND
X
X
X
X
Disabled
No operation until reset goes high. Enters monitor mode. PTC0, PTC1, and PTC3 voltages only required if IRQ = VTST; PTC3 determines frequency divider. Exit monitor mode by POR or by RST low then high Enters monitor mode. PTC0, PTC1, and PTC3 voltages only required if IRQ = VTST; PTC3 determines frequency divider. Exit monitor mode by POR or by RST low then high Enters monitor mode. External frequency always divided by 4. Exit monitor mode by POR only. Enters user mode.
VTST
VDD or VTST
X
0
0
1
0
0
4.9152 MHz
2.4576 MHz
Disabled
9600
VTST
VDD or VTST
X
1
0
1
0
0
9.8304 MHz
2.4576 MHz
Disabled
9600
VDD or GND
VDD
Blank "$FFFF"
X
X
X
0
0
9.8304 MHz
2.4576 MHz
Disabled
9600
VDD or GND
VDD
Not Blank
X
X
X
X
X
X
--
Enabled
--
Notes:
Monitor ROM (MON) Functional Description
1. PTA7 = 0 if serial communication; PTA7 = 1 if parallel communication 2. External clock is derived by a 4.9152/9.8304 MHz crystal or off-chip oscillator
Monitor ROM (MON)
Monitor mode uses different vectors for reset and SWI. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. When the host computer has completed downloading code into the MCU RAM, This code can be executed by driving PTA0 low while asserting RST low and then high. The internal monitor ROM firmware will interpret the low on PTA0 as an indication to jump to RAM, and execution control will then continue from RAM. Execution of an SWI from the downloaded code will return program control to the internal monitor ROM firmware. Alternatively, the host can send a RUN command, which executes an RTI, and this can be used to send control to the address on the stack pointer. The COP module is disabled in monitor mode as long as VTST is applied to the IRQ or the RST pin. (See Section 9. System Integration Module (SIM) for more information on modes of operation.) Table 10-2 is a summary of the differences between user mode and monitor mode. Table 10-2. Mode Differences
Functions Modes COP Enabled
Disabled (1)
Reset Vector High $FFFE $FEFE
Reset Vector Low $FFFF $FEFF
SWI Vector High $FFFC $FEFC
SWI Vector Low $FFFD $FEFD
User Monitor
Notes: 1. If the high voltage (VTST) is removed from the IRQ pin, the SIM asserts its COP enable output. The COP is an option enabled or disabled by the COPD bit in the configuration register.
10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 10-2 and Figure 10-3.)
Data Sheet 142 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Monitor ROM (MON) Functional Description
START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
NEXT START BIT
Figure 10-2. Monitor Data Format
NEXT START BIT
$A5
START BIT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT STOP BIT
BREAK
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 10-3. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8 kbaud. Transmit and receive baud rates must be identical. 10.4.3 Echoing As shown in Figure 10-4, the monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking.
SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Figure 10-4. Read Transaction Any result of a command appears after the echo of the last byte of the command. 10.4.4 Break Signal A start bit followed by nine low bits is a break signal (see Figure 10-5). When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Monitor ROM (MON)
Data Sheet 143
Monitor ROM (MON)
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 10-5. Break Transaction
10.4.5 Commands The monitor ROM uses the following commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
Table 10-3. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
ECHO
RETURN
Data Sheet 144 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Monitor ROM (MON) Functional Description
Table 10-4. WRITE (Write Memory) Command
Description Operand Data Returned Opcode Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49 Command Sequence
SENT TO MONITOR
WRITE
WRITE
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 10-5. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read Next 2 Bytes in Memory from Last Address Accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence
SENT TO MONITOR
IREAD
IREAD
DATA
DATA
ECHO
RETURN
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Monitor ROM (MON)
Data Sheet 145
Monitor ROM (MON)
Table 10-6. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Specifies single data byte None $19 Command Sequence
SENT TO MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64K-byte memory map. Table 10-7. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C Command Sequence
SENT TO MONITOR
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
Data Sheet 146 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Monitor ROM (MON) Functional Description
Table 10-8. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes RTI instruction None None $28 Command Sequence
SENT TO MONITOR
RUN
RUN
ECHO
10.4.6 Baud Rate The communication baud rate is controlled by crystal frequency and the state of the PTC3 pin upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the PTC3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 10-9. Monitor Baud Rate Selection
Crystal Frequency 9.8304 MHz 9.8304 MHz PTC3 Pin 0 1 Baud Rate 19200 bps 9600 bps
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Monitor ROM (MON)
Data Sheet 147
Monitor ROM (MON)
Data Sheet 148 Monitor ROM (MON)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 11. Timer Interface Module (TIM)
11.1 Contents
11.2 11.3 11.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 154 11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .155 11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 155 11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 156 11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 157 11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.8 11.9 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 161 11.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 163 11.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 164 11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 165 11.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 168
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 149
Timer Interface Module (TIM) 11.2 Introduction
This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIM.
11.3 Features
Features of the TIM include the following: * Two input capture/output compare channels - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIM clock input - Seven-frequency internal bus clock prescaler selection Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
* * * * *
NOTE:
TCH1 (timer channel 1) is not bonded to an external pin on this MCU. Therefore, any references to the timer TCH1 pin in the following text should be interpreted as not available -- but the internal status and control registers are still available.
11.4 Pin Name Conventions
The TIM shares the TCH0 pin with the sync processor CLAMP output. Table 11-1. Pin Name Conventions
TIM Generic Pin Name: Full TIM Pin Name: Pin Selected for TCH0 By: TCH0 CLAMP/TCH0 ELS0B:ELS0A
Data Sheet 150 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) Functional Description
11.5 Functional Description
Figure 11-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels.
PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 (Not available) CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 11-1. TIM Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 151
Timer Interface Module (TIM)
Addr.
Register Name Read: TIM Status and Control Register Write: (TSC) Reset: Read: TIM Counter Register High Write: (TCNTH) Reset: Read: TIM Counter Register Low Write: (TCNTL) Reset: Read: TIM Counter Modulo Register High Write: (TMODH) Reset: Read: TIM Counter Modulo Register Low Write: (TMODL) Reset: TIM Channel 0 Read: Status and Control Write: Register (TSC0) Reset: Read: TIM Channel 0 Register High Write: (TCH0H) Reset: Read: TIM Channel 0 Register Low Write: (TCH0L) Reset: TIM Channel 1 Read: Status and Control Write: Register (TSC1) Reset:
Bit 7 TOF
6 TOIE
5 TSTOP
4 0 TRST
3 0
2 PS2
1 PS1 0 Bit9
Bit 0 PS0 0 Bit8
$000A
0 0 Bit15 0 Bit14 1 Bit13
0 Bit12
0 Bit11
0 Bit10
$000C
0 Bit7
0 Bit6
0 Bit5
0 Bit4
0 Bit3
0 Bit2
0 Bit1
0 Bit0
$000D
0 Bit15 1 Bit7 1 CH0F
0 Bit14 1 Bit6 1 CH0IE
0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 1 Bit0 1
CH0MAX
$000E
$000F
$0010
0 0 Bit15 0 Bit14 0 Bit8
$0011
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0012
Indeterminate after reset CH1F CH1IE 0 0 0 0 0 0 0 0 0 0 MS1A ELS1B ELS1A TOV1
CH1MAX
$0013
Data Sheet 152 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) Functional Description
Addr.
Register Name Read: TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset:
Bit 7 Bit15
6 Bit14
5 Bit13
4 Bit12
3 Bit11
2 Bit10
1 Bit9
Bit 0 Bit8
$0014
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0015
Indeterminate after reset = Unimplemented
11.5.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.
11.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
11.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 153
Timer Interface Module (TIM)
11.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
Data Sheet 154 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) Functional Description
11.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
11.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 11-2 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM to set the pin if the state of the PWM pulse is logic zero.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 155
Timer Interface Module (TIM)
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 11-2. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 11.10.1 TIM Status and Control Register (TSC)). The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 11.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 11.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.
Data Sheet 156 Timer Interface Module (TIM) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) Functional Description
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
11.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 157
Timer Interface Module (TIM)
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
11.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 11-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 11-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Data Sheet 158 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output.TIM channel 0 status and control register (TSC0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).
11.6 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1. CHxF and CHxIE are in the TIM channel x status and control register.
*
11.7 Low-Power Modes
The WAIT and STOP instructions puts the MCU in low-powerconsumption standby modes. 11.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 159
Timer Interface Module (TIM)
11.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exit stop mode after an external interrupt.
11.8 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 23.6.4 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.
11.9 I/O Signals
The TIM channel I/O pin is CLAMP/TCH0. The pin is shared with sync processor CLAMP output signal. TCH0 pin is programmable independently as an input capture pin or an output compare pin. It also can be configured as a buffered output compare or buffered PWM pin.
Data Sheet 160 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) I/O Registers
11.10 I/O Registers
The following I/O registers control and monitor operation of the TIM: * * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
11.10.1 TIM Status and Control Register (TSC) The TIM status and control register does the following: * * * * *
Address:
Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
$000A Bit 7 6 TOIE 5 TSTOP TRST 0 1 0 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
Read: Write: Reset:
TOF 0 0
= Unimplemented
Figure 11-3. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic zero to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 161
Timer Interface Module (TIM)
effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic one to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic zero. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 11-2 shows. Reset clears the PS[2:0] bits.
Data Sheet 162 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) I/O Registers
Table 11-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal Bus Clock / 1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 Not available
11.10.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Address: $000C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit15 TCNTH 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8
Address:
$000D Bit 7
TCNTL 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0
Read: Write: Reset:
Bit7
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-4. TIM Counter Registers (TCNTH:TCNTL)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 163
Timer Interface Module (TIM)
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
11.10.3 TIM Counter Modulo Registers (TMODH:TMODL) The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $000E Bit 7 Read: Bit15 Write: Reset: 1 1 1 1 1 1 1 1 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TMODH 6 5 4 3 2 1 Bit 0
Address:
$000F Bit 7
TMODL 6 Bit6 1 5 Bit5 1 4 Bit4 1 3 Bit3 1 2 Bit2 1 1 Bit1 1 Bit 0 Bit0 1
Read: Bit7 Write: Reset: 1
Figure 11-5. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
Data Sheet 164 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) I/O Registers
11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: * * * * * * * *
Address:
Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
$0010 Bit 7 TSC0 6 CH0IE 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0
CH0MAX
Read: Write: Reset:
CH0F 0 0 0 0
Address:
$0013 Bit 7
TSC1 6 CH1IE 5 0 MS1A 0 0 ELS1B 0 ELS1A 0 TOV1 0
CH1MAX
4
3
2
1
Bit 0
Read: Write: Reset:
CH1F 0 0 0
0
= Unimplemented
Figure 11-6. TIM Channel Status and Control Registers (TSC0:TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 165
Timer Interface Module (TIM)
an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:A 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 11-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 11-3.) Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
Data Sheet 166 Timer Interface Module (TIM) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) I/O Registers
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELS0B and ELS0A are both clear, channel 0 is not connected to the CLAMP/TCH0 pin. The pin is available as the CLAMP output of the sync processor. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 11-3. Mode, Edge, and Level Selection
MSxB
X X 0 0 0 0 0 0 1 1 1
MSxA
0 1 0 0 0 1 1 1 X X X
ELSxB
0 0 0 1 1 0 1 1 0 1 1
ELSxA
0
Mode
Output Preset
Configuration
Pin is CLAMP of sync processor(1); Initial Output Level High Pin is CLAMP of sync processor(1); Initial Output Level Low Capture on Rising Edge Only
0 1 0 1 1 0 1 1 0 1 Output Compare or PWM Input Capture
Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare
Buffered Toggle Output on Compare Output Clear Output on Compare Compare or Buffered Set Output on Compare PWM
Notes: 1. For CLAMP/TCH0 pin only.
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 167
Timer Interface Module (TIM)
TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic one, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 11-7 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD OVERFLOW OVERFLOW OVERFLOW OVERFLOW
TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 11-7. CHxMAX Latency 11.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.
Data Sheet 168 Timer Interface Module (TIM) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Timer Interface Module (TIM) I/O Registers
In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0011 Bit 7 Read: Bit15 Write: Reset: Indeterminate after reset Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCH0H 6 5 4 3 2 1 Bit 0
Address:
$0012 Bit 7
TCH0L 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0
Read: Bit7 Write: Reset: Indeterminate after reset
Address:
$0014 Bit 7
TCH1H 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8
Read: Bit15 Write: Reset: Indeterminate after reset
Address:
$0015 Bit 7
TCH1L 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0
Read: Bit7 Write: Reset: Indeterminate after reset
Figure 11-8. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Timer Interface Module (TIM)
Data Sheet 169
Timer Interface Module (TIM)
Data Sheet 170 Timer Interface Module (TIM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 12. Pulse Width Modulator (PWM)
12.1 Contents
12.2 12.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.4.1 PWM Data Registers 0 to 7 (0PWM-7PWM). . . . . . . . . . . 173 12.4.2 PWM Control Register (PWMCR) . . . . . . . . . . . . . . . . . . . 174
12.2 Introduction
Eight 8-bit PWM channels are available on the MC68HC908LD64. Channels 0 to 7 are shared with port-B I/O pins under the control of the PWM control register.
12.3 Functional Description
Each 8-Bit PWM channel is composed of an 8-bit register which contains a 5-bit PWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. There are eight PWM data registers, controlling each PWM channel. The value programmed in the 5-bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM portion is the system bus clock, the repetition rate of the output is hence 187.5kHz at 6MHz clock. The 3-bit BRM will generate a number of narrow pulses which are equally distributed among an 8-PWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Example of the waveforms are shown in Figure 12-4.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Pulse Width Modulator (PWM)
Data Sheet 171
Pulse Width Modulator (PWM)
Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and N is the content of the 3-bit BRM portion. Using this mechanism, a true 8-bit resolution PWM type DAC with reasonably high repetition rate can be obtained. The value of each PWM data register is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin. Double buffering is not used in this PWM design.
Addr. $0070
Register Name PWM0 Data Register (0PWM) PWM1 Data Register (1PWM) PWM2 Data Register (2PWM) PWM3 Data Register (3PWM) PWM4 Data Register (4PWM) PWM5 Data Register (5PWM) PWM6 Data Register (6PWM) PWM7 Data Register (7PWM) PWM Control Register (PWMCR) Read:
Bit 7 0PWM4 Write: Read: 1PWM4 Write: Read: 2PWM4 Write: Read: 3PWM4 Write: Read: 4PWM4 Write: Read: 5PWM4 Write: Read: 6PWM4 Write: Read: 7PWM4 Write: Read: PWM7E Write: Reset: 0
6 0PWM3
5 0PWM2
4 0PWM1
3 0PWM0
2 0BRM2
1 0BRM1
Bit 0 0BRM0
$0071
1PWM3
1PWM2
1PWM1
1PWM0
1BRM2
1BRM1
1BRM0
$0072
2PWM3
2PWM2
2PWM1
2PWM0
2BRM2
2BRM1
2BRM0
$0073
3PWM3
3PWM2
3PWM1
3PWM0
3BRM2
3BRM1
3BRM0
$0074
4PWM3
4PWM2
4PWM1
4PWM0
4BRM2
4BRM1
4BRM0
$0075
5PWM3
5PWM2
5PWM1
5PWM0
5BRM2
5BRM1
5BRM0
$0076
6PWM3
6PWM2
6PWM1
6PWM0
6BRM2
6BRM1
6BRM0
$0077
7PWM3
7PWM2
7PWM1
7PWM0
7BRM2
7BRM1
7BRM0
$0078
PWM6E 0
PWM5E 0
PWM4E 0
PWM3E 0
PWM2E 0
PWM1E 0
PWM0E 0
Figure 12-1. PWM I/O Register Summary
Data Sheet 172 Pulse Width Modulator (PWM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Pulse Width Modulator (PWM) PWM Registers
12.4 PWM Registers
The PWM module uses of nine registers for data and control functions. * * PWM data registers ($0070-$0077) PWM control register ($0078)
12.4.1 PWM Data Registers 0 to 7 (0PWM-7PWM)
Address: $0070-$0077 Bit 7 Read: xPWM4 Write: Reset: 0 0 0 0 0 0 0 0 xPWM3 xPWM2 xPWM1 xPWM0 xBRM2 xBRM1 xBRM0 6 5 4 3 2 1 Bit 0
Figure 12-2. PWM Data Registers 0 to 7 (0PWM-7PWM) The output waveform of the eight PWM channels are each configured by an 8-bit register, which contains a 5-bit PWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion xPWM4-xPWM0 -- PWM Bits The value programmed in the 5-bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM portion is the system bus clock, the repetition rate of the output is hence fOP / 32. Examples of PWM output waveforms are shown in Figure 12-4. xBRM2-xBRM0 -- Binary Rate Multiplier Bits The 3-bit BRM will generate a number of narrow pulses which are equally distributed among an 8-PWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Examples of PWM output waveforms are shown in Figure 12-4.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Pulse Width Modulator (PWM)
Data Sheet 173
Pulse Width Modulator (PWM)
12.4.2 PWM Control Register (PWMCR)
Address: $0078 Bit 7 Read: PWM7E Write: Reset: 0 0 0 0 0 0 0 0 PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E 6 5 4 3 2 1 Bit 0
Figure 12-3. PWM Control Register (PWMCR) PWM7E-PWM0E -- PWM Output Enable Setting a bit to 1 will enable the corresponding PWM channel to use as PWM output. A zero configures the corresponding PWM pin as a standard I/O port pin. Reset clears these bits. 1 = Port pin configured as PWM output 0 = Port pin configured as standard I/O port pin. Table 12-1. PWM Channels and Port I/O pins
Port Pin PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PWM Channel PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Control Bit PWM0E PWM1E PWM2E PWM3E PWM4E PWM5E PWM6E PWM7E
Data Sheet 174 Pulse Width Modulator (PWM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Pulse Width Modulator (PWM) PWM Registers
1 PWM cycle = 32T M=$00
T M=$01 31T
M=$0F
16T
16T
M=$1F
31T Pulse inserted at end of PWM cycle depends on setting of N.
T
T=1 CPU clock period (0.167ms if CPU clock=6MHz) M = value set in 5-bit PWM (bit3-bit7) N = value set in 3-bit BRM (bit0-bit2)
N xx1 x1x 1xx
PWM cycles where pulses are inserted in a 8-cycle frame 4 2, 6 1, 3, 5, 7
Number of inserted pulses in a 8-cycle frame 1 2 4
Figure 12-4. 8-Bit PWM Output Waveforms
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Pulse Width Modulator (PWM)
Data Sheet 175
Pulse Width Modulator (PWM)
Data Sheet 176 Pulse Width Modulator (PWM)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 13. Analog-to-Digital Converter (ADC)
13.1 Contents
13.2 13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.1 ADC Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . 182 13.7.2 ADC Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . .182 13.7.3 ADC Voltage Reference High Pin (VRH) . . . . . . . . . . . . . . 182 13.7.4 ADC Voltage Reference Low Pin (VRL). . . . . . . . . . . . . . . 182 13.7.5 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .183 13.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Analog-to-Digital Converter (ADC)
Data Sheet 177
Analog-to-Digital Converter (ADC) 13.2 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is a 6-channel 8-bit successive approximation ADC.
13.3 Features
Features of the ADC module include: * * * * *
Addr. Register Name Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: $003C ADC Data Register Write: (ADR) Reset: Read: $003D ADC Input Clock Register Write: (ADICLK) Reset: ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0
Six channels with multiplexed input Linear successive approximation 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt
Bit 7 COCO AIEN 0 AD7 0 AD6 ADCO 0 AD5 ADCH4 1 AD4 ADCH3 1 AD3 ADCH2 1 AD2 ADCH1 1 AD1 ADCH0 1 AD0 6 5 4 3 2 1 Bit 0
$003B
Indeterminate after reset 0 0 0 0 0
= Unimplemented
Figure 13-1. ADC I/O Register Summary
Data Sheet 178 Analog-to-Digital Converter (ADC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Analog-to-Digital Converter (ADC) Functional Description
13.4 Functional Description
Six ADC channels are available for sampling external sources at pins PTC5-PTC0. An analog multiplexer allows the single ADC converter to select one of the six ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 13-2 shows a block diagram of the ADC.
INTERNAL DATA BUS READ DDRC WRITE DDRC RESET WRITE PTC PTCx DDRCx DISABLE
PTCx/ADCx
READ PTC
ADC DATA REGISTER
DISABLE
ADC CHANNEL x
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC
ADC VOLTAGE IN ADCVIN
CHANNEL SELECT (1 OF 6 CHANNELS)
ADCH[4:0]
AIEN
COCO
ADC CLOCK CLOCK GENERATOR
BUS CLOCK
ADIV[2:0]
Figure 13-2. ADC Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 179
Analog-to-Digital Converter (ADC)
13.4.1 ADC Port I/O Pins PTC5/ADC5-PTC0/ADC0 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits, ADCH[4:0], in the ADC status and control register define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
13.4.2 Voltage Conversion When the input voltage to the ADC equals to VRH, the ADC converts the signal to $FF (full scale). If the input voltage equals to VRL, the ADC converts it to $00. Input voltages between VRH and VRL is a straight-line linear conversion. All other input voltages will result in $FF if greater than VRH and $00 if less than VRL.
NOTE:
Input voltage should not exceed the analog supply voltages.
13.4.3 Conversion Time Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1MHz, then one conversion will take 16s to complete. With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz. Conversion time = 16 to17 ADC cycles ADC frequency
Number of bus cycles = conversion time x bus frequency
Data Sheet 180 Analog-to-Digital Converter (ADC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Analog-to-Digital Converter (ADC) Interrupts
13.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The conversion complete bit, COCO, in the ADC status and control register is set after each conversion and can be cleared by writing to the ADC status and control register or reading of the ADC data register.
13.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes.
13.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The interrupt vector is defined in Table 2-1 . Vector Addresses.
13.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low-power consumption standby modes.
13.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1's before executing the WAIT instruction.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Analog-to-Digital Converter (ADC)
Data Sheet 181
Analog-to-Digital Converter (ADC)
13.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode.
13.7 I/O Signals
The ADC module has six channels that are shared with port C I/O pins, PTC5/ADC5-PTC0/ADC0. 13.7.1 ADC Analog Power Pin (VDDA) The ADC analog portion uses VDDA as its power pin. Connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results.
NOTE:
Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
13.7.2 ADC Analog Ground Pin (VSSA) The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. 13.7.3 ADC Voltage Reference High Pin (VRH) VRH is the high voltage reference for the ADC. 13.7.4 ADC Voltage Reference Low Pin (VRL) VRL is the low voltage reference for the ADC. 13.7.5 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the six ADC channels to the ADC module.
Data Sheet 182 Analog-to-Digital Converter (ADC) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Analog-to-Digital Converter (ADC) I/O Registers
13.8 I/O Registers
Three I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC input clock register (ADICLK)
13.8.1 ADC Status and Control Register Function of the ADC status and control register is described here.
Address: $003B Bit 7 Read: Write: Reset: 0 0 0 1 1 1 1 1 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 13-3. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written, or whenever the ADC data register is read. Reset clears this bit. When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be logic 0 when read. 1 = conversion completed (AIEN = 0) 0 = conversion not completed (AIEN = 0) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status and control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 183
Analog-to-Digital Converter (ADC)
ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels or reference voltages. The five channel select bits are detailed in the Table 13-1.
NOTE:
Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. Recovery from the disabled state requires one conversion cycle to stabilize. Table 13-1. MUX Channel Select
NOTE:
ADCH4 0 0 0 0 0 0 0 1 1 1 1 1 1
Notes:
ADCH3 0 0 0 0 0 0 0 1 1 1 1 1 1
ADCH2 0 0 0 0 1 1 1 0 0 1 1 1 1
ADCH1 0 0 1 1 0 0 1 1 1 0 0 1 1
ADCH0 0 1 0 1 0 1 0 0 1 0 1 0 1
ADC Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5
Input Select PTC0/ADC0 PTC1/ADC1 PTC2/ADC2 PTC3/ADC3 PTC4/ADC4 PTC5/ADC5 Unused(1)
--
-- --
Reserved Unused VRH VRL ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown. Data Sheet 184 Analog-to-Digital Converter (ADC) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Analog-to-Digital Converter (ADC) I/O Registers
13.8.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes.
Address: $003C Bit 7 Read: Write: Reset: = Unimplemented Indeterminate after reset AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
Figure 13-4. ADC Data Register (ADR)
13.8.3 ADC Input Clock Register The ADC input clock register (ADICLK) selects the clock frequency for the ADC.
Address: $003D Bit 7 Read: ADIV2 Write: Reset: 0 0 0 0 0 0 0 0 ADIV1 ADIV0 6 5 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 13-5. ADC Input Clock Register (ADICLK) ADIV[2:0] -- ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 13-2 shows the available clock configurations. The ADC clock should be set to approximately 1MHz.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Analog-to-Digital Converter (ADC)
Data Sheet 185
Analog-to-Digital Converter (ADC)
Table 13-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 X = don't care ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC Input Clock / 1 ADC Input Clock / 2 ADC Input Clock / 4 ADC Input Clock / 8 ADC Input Clock / 16
Data Sheet 186 Analog-to-Digital Converter (ADC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 14. Universal Serial Bus Module (USB)
14.1 Contents
14.2 14.3 14.4 14.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
14.6 Hub Function I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.6.1 USB Hub Root Port Control Register (HRPCR) . . . . . . . . . 194 14.6.2 USB Hub Downstream Port Control Registers (HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.6.3 USB SIE Timing Interrupt Register (SIETIR) . . . . . . . . . . . 198 14.6.4 USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . . 200 14.6.5 USB Hub Address Register (HADDR) . . . . . . . . . . . . . . . . 202 14.6.6 USB Hub Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . . 203 14.6.7 USB Hub Control Register 0 (HCR0) . . . . . . . . . . . . . . . . . 205 14.6.8 USB Hub Endpoint 1 Control and Data Register (HCDR) . 206 14.6.9 USB Hub Status Register (HSR) . . . . . . . . . . . . . . . . . . . . 208 14.6.10 USB Hub Endpoint 0 Data Registers (HE0D0-HE0D7). . . 209 14.7 Embedded Device Function I/O Registers . . . . . . . . . . . . . . . 209 14.7.1 USB Embedded Device Address Register (DADDR). . . . . 210 14.7.2 USB Embedded Device Interrupt Register 0 (DIR0) . . . . . 210 14.7.3 USB Embedded Device Interrupt Register 1 (DIR1) . . . . . 212 14.7.4 USB Embedded Device Control Register 0 (DCR0) . . . . . 213 14.7.5 USB Embedded Device Control Register 1 (DCR1) . . . . . 215 14.7.6 USB Embedded Device Control Register 2 (DCR2) . . . . . 216 14.7.7 USB Embedded Device Status Register (DSR) . . . . . . . . . 217 14.7.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.7.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 187
Universal Serial Bus Module (USB) 14.2 Introduction
This section describes the Universal Serial Bus (USB) module. This MC68HC908LD64's USB module supports both embedded full-speed device and hub functions with one upstream port and four downstream ports.
14.3 Features
Features of the USB module include the following: * * Integrated USB transceiver supporting both full-speed and low-speed functions USB data control logic - Packet decoding/generation - CRC generation and checking - NRZI encoding/decoding - Bit-stuffing * * * * USB reset support Suspend and resume operations Remote wakeup support STALL, NAK, and ACK handshake generation
Features of the hub function include the following: * Hub control endpoint 0 - 8-byte transmit buffer - 8-byte receive buffer * Hub interrupt endpoint 1 - 1-byte transmit buffer * USB interrupts - Transaction interrupt driven - Start of frame interrupt
Data Sheet 188 Universal Serial Bus Module (USB) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) I/O Pins
- EOF2 interrupt - End of packet interrupt - Signal transition interrupt - Frame timer locked interrupt * Hub repeater and controller function - Downstream and upstream connectivity - Bus state evaluation - Selective reset, suspend and resume - Fault condition hardware detection Features of the embedded device function include the following: * Device control endpoint 0 - 8-byte transmit buffer - 8-byte receive buffer * Device interrupt endpoints 1 and 2 - 8-byte transmit buffer * USB generated interrupts - transaction interrupt driven
14.4 I/O Pins
The USB module uses ten I/O pin (five pairs), with two dedicated pins for the upstream port pair and eight shared port I/O pins for the downstream ports. The full name of the USB I/O pins are listed in Table 14-1. The generic pin name appear in the text that follows.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 189
Universal Serial Bus Module (USB)
Table 14-1. USB I/O Pins
USB Generic Pin Names: D0+ D0- D1+ D1- D2+ D2- D3+ D3- D4+ D4- Full MCU Pin Names: DPLUS0 -- DMINUS0 PTE0/DPLUS1 USBDS1E bit in PECR ($0068) PTE1/DMINUS1 PTE2/DPLUS2 USBDS2E bit in PECR ($0068) PTE3/DMINUS2 PTE4/DPLUS3 USBDS3E bit in PECR ($0068) PTE5/DMINUS3 PTE6/DPLUS4 USBDS4E bit in PECR ($0068) PTE7/DMINUS4 Pin Selected for USB Function By:
Addr. $0020 to $0027 $0028 to $002F $0030 to $0037
Register Name
Bit 7
6 DE0Rx6 DE0Tx6
5 DE0Rx5 DE0Tx5
4 DE0Rx4 DE0Tx4
3 DE0Rx3 DE0Tx3
2 DE0Rx2 DE0Tx2
1 DE0Rx1 DE0Tx1
Bit 0 DE0Rx0 DE0Tx0
USB Embedded Device Read: DE0Rx7 Endpoint 0 Data Write: DE0Tx7 Register 0 to 7 (DE0D0 to DE0D7) Reset: USB Embedded Device Read: Endpoint 1/2 Data Write: DE1Tx7 Register 0 to 7 (DE1D0 to DE1D7) Reset: Read: HE0Rx7 USB Hub Endpoint 0 Data Register 0 to 7 Write: HE0Tx7 (HE0D0 to HE0D7) Reset: Read: USB Embedded Device Control Register 2 Write: (DCR2) Reset: 0 0
Indeterminate after reset
DE1Tx6
DE1Tx5
DE1Tx4
DE1Tx3
DE1Tx2
DE1Tx1
DE1Tx0
Indeterminate after reset HE0Rx6 HE0Tx6 0 0 DADD6 0 HE0Rx5 HE0Tx5 0 0 DADD5 0 HE0Rx4 HE0Tx4 0 0 DADD4 0 HE0Rx3 HE0Tx3 HE0Rx2 HE0Tx2 HE0Rx1 HE0Tx1 HE0Rx0 HE0Tx0
Indeterminate after reset ENABLE2 ENABLE1 DSTALL2 DSTALL1 0 DADD3 0 0 DADD2 0 0 DADD1 0 0 DADD0 0
$0047
$0048
Read: USB Embedded Device DEVEN Address Register Write: (DADDR) Reset: 0
X = Indeterminate
= Unimplemented
Figure 14-1. USB I/O Register Summary
Data Sheet 190 Universal Serial Bus Module (USB) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) I/O Pins
$0049
Read: TXD0F USB Embedded Device Interrupt Register 0 Write: (DIR0) Reset: 0 Read: TXD1F USB Embedded Device Interrupt Register 1 Write: (DIR1) Reset: 0 Read: USB Embedded Device T0SEQ Control Register 0 Write: (DCR0) Reset: 0 Read: USB Embedded Device T1SEQ Control Register 1 Write: (DCR1) Reset: 0 USB Embedded Device Read: DRSEQ Status Register Write: (DSR) Reset: 0 USB Hub Downstream Read: Port 1 Control Register Write: (HDP1CR) Reset: USB Hub Downstream Read: Port 2 Control Register Write: (HDP2CR) Reset: USB Hub Downstream Read: Port 3 Control Register Write: (HDP3CR) Reset: USB Hub Downstream Read: Port 4 Control Register Write: (HDP4CR) Reset: PEN1 0 PEN2 0 PEN3 0 PEN4 0 SOFF 0 RSTF 0*
RXD0F 0 0 0 DSTALL0 0 ENDADD 0 DSETUP 0 LOWSP1 0 LOWSP2 0 LOWSP3 0 LOWSP4 0 EOF2F 0 0 RSTFR 0
0 0 0 0 TX0E 0 TX1E 0 DTX1ST 0 RST1 0 RST2 0 RST3 0 RST4 0 EOPF 0 LOCKF 0
0 0 0 0 RX0E 0 0 0 0 DTX1STR 0 RESUM1 0 RESUM2 0 RESUM3 0 RESUM4 0 TRANF 0 0 LOCKFR 0
TXD0IE 0 TXD1IE 0 TP0SIZ3 0 TP1SIZ3 0 RP0SIZ3 0 SUSP1 0 SUSP2 0 SUSP3 0 SUSP4 0 SOFIE 0 0 SOFFR 0
RXD0IE 0 0 0 TP0SIZ2 0 TP1SIZ2 0 RP0SIZ2 0 0 0 0 0 0 0 0 0 EOF2IE 0 0 EOF2FR 0
0 TXD0FR 0 0 TXD1FR 0 TP0SIZ1 0 TP1SIZ1 0 RP0SIZ1 0 D1+ X D2+ X D3+ X D4+ X EOPIE 0 0 EOPFR 0
0 RXD0FR 0 0 0 TP0SIZ0 0 TP1SIZ0 0 RP0SIZ0 0 D1- X D2- X D3- X D4- X TRANIE 0 0 TRANFR 0
$004A
$004B
$004C
$004D
$0051
$0052
$0053
$0054
USB SIE Timing Interrupt Read: $0056 Register Write: (SIETIR) Reset: $0057 USB SIE Timing Status Read: Register Write: (SIETSR) Reset:
X = Indeterminate
= Unimplemented
Figure 14-1. USB I/O Register Summary
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 191
Universal Serial Bus Module (USB)
$0058
Read: USB Hub Address USBEN Register Write: (HADDR) Reset: 0* Read: USB Hub Interrupt Register 0 Write: (HIR0) Reset: Read: USB Hub Control Register 0 Write: (HCR0) Reset: TXDF 0 TSEQ 0
ADD6 0 RXDF 0 STALL0 0 PNEW 0 SETUP X 0 0
ADD5 0 0 0 TXE 0 PCHG5 0 TX1ST X 0 0
ADD4 0 0 0 RXE 0 PCHG4 0 0 TX1STR 0
ADD3 0
ADD2 0
ADD1 0 0 TXDFR 0 TPSIZ1 0 PCHG1 0 RPSIZ1 X D0+ X
ADD0 0 0 RXDFR 0 TPSIZ0 0 PCHG0 0 RPSIZ0 X D0- X
* RSTF and USBEN are reset by a power-on reset (POR) only. $0059 TXDIE 0 TPSIZ3 0 PCHG3 0 RPSIZ3 X RXDIE 0 TPSIZ2 0 PCHG2 0 RPSIZ2 X 0 0
$005B
USB Hub Endpoint 1 Read: STALL1 $005C Control and Data Register Write: (HCDR) Reset: 0 Read: USB Hub Status Register $005D Write: (HSR) Reset: $005E USB Hub Root Port Read: Control Register Write: (HRPCR) Reset: RSEQ X 0 0
RESUM0 SUSPND 0 0
X = Indeterminate
= Unimplemented
Figure 14-1. USB I/O Register Summary
14.5 Overview
This USB module is designed to serve as a compound device. An embedded full-speed device function is combined with a hub in a single USB module. For the hub sub-module, five basic properties can be supported by the hardware or the software: connectivity behavior, power management, device connect/disconnect detection, bus fault detection and recovery, and full/low-speed device traffic control. Endpoint 0 of the hub submodule functions as a receive/transmit control endpoint. Endpoint 1 of the hub sub-module functions as interrupt transfer to report the device change state.
Data Sheet 192 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Overview
For the embedded device sub-module, three types of USB data transfers are supported: control, interrupt, and bulk (transmit only). Endpoint 0 of the embedded device sub-module functions as a receive/transmit control endpoint. Endpoints 1 and 2 of the embedded device sub-module can function as interrupt or bulk, but only in the transmit direction. The block diagram of the USB module is shown Figure 14-2. The USB module manages communications between the host and the USB function. The module is partitioned into eight functional blocks. These blocks consist of a dual function transceiver, the hub repeater function, the serial interface engine (SIE), the frame counter logic, the hub control logic, the embedded device control logic, and the endpoint registers.
CPU BUS
EMBEDDED DEVICE CONTROL LOGIC
ENDPOINT 0 (CONTROL ENDPOINT) 8-BYTE TRANSMIT BUFFER 8-BYTE RECEIVE BUFFER ENDPOINT 1/2 (INTERRUPT/BULK ENDPOINT) 8-BYTE TRANSMIT BUFFER
HUB CONTROL LOGIC
ENDPOINT 0 (CONTROL ENDPOINT) 8-BYTE TRANSMIT BUFFER 8-BYTE RECEIVE BUFFER ENDPOINT 1 (INTERRUPT ENDPOINT) 8-BYTE TRANSMIT BUFFER
REGISTERS
OSCOUT FROM OSC
12MHz
FRAME COUNTER
SERIAL INTERFACE ENGINE
HUB REPEATER
48MHz TRANSCEIVER TRANSCEIVER
CLOCK DOUBLER
24MHz OSCXCLK FROM OSC
D4+ D4-
D3+ D3-
D2+ D2-
D1+ D1-
D0+ D0- ROOT PORT
DOWNSTREAM PORTS
Figure 14-2. USB Module Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 193
Universal Serial Bus Module (USB) 14.6 Hub Function I/O Registers
The USB hub function provides a set of control/status registers and sixteen data registers that provide storage for the buffering of data between the USB hub function and the CPU.
14.6.1 USB Hub Root Port Control Register (HRPCR)
Address: $005E Bit 7 Read: Write: Reset: 0 0 0 0 0 0 X X 0 6 0 5 0 RESUM0 SUSPND 4 3 2 0 1 D0+ Bit 0 D0-
X = Indeterminate
= Unimplemented
Figure 14-3. USB Hub Root Port Control Register (HRPCR) RESUM0 -- Force Resume to the Root Port This read/write bit forces a resume signal (K state) onto the USB root port data lines to initiate a remote wakeup. Software should control the timing of the forced resume to be between 10ms and 15ms. Reset clears this bit. 1 = Force root port data lines to K state 0 = Default SUSPND -- USB Suspend Control Bit To save power, this read/write bit should be set by the software if a constant idle state for more than 3ms is detected on the USB bus. Setting this bit puts the transceiver into a power savings mode. This bit also determines the latch scheme for the data lines of the root port and the downstream port. When this bit is 1, the current state shown on the data lines will be reflected to the data register (D+/D-) directly. When the bit is 0, the data registers are the latched state sampled at the last EOF2 sample point. The hub repeater's function is affected by this bit too. The upstream and downstream traffic will be blocked if this bit is set to 1. When the global resume or the downstream remote wakeup signal is found by the suspended hub,
Data Sheet 194 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
software is responsible to propagate the traffic between the root port and the enabled downstream port by setting the RESUMx control bit. Reset clears this bit. EOF2 is generated by the MCU every millisecond, if SOF is not detected when three or more EOF2 have occurred, software can set the SUSPND bit and put the MCU into suspend mode. D0+, D0- -- Root Port Differential Data These read-only bits are the differential data shown on the hub root ports. When the SUSPND bit is 0, the data is the latched state at the last EOF2 sample point. When the SUSPND bit is 1, the data reflects the current state on the data line while accessing this register.
14.6.2 USB Hub Downstream Port Control Registers (HDP1CR-HDP4CR)
Address: $0051-$0054 Bit 7 Read: PEN1 Write: Read: PEN2 Write: Read: PEN3 Write: Read: PEN4 Write: Reset: 0 0 0 0 0 0 X X LOWSP4 RST4 RESUM4 SUSP4 0 D4+ D4- LOWSP3 RST3 RESUM3 SUSP3 0 D3+ D3- LOWSP2 RST2 RESUM2 SUSP2 0 D2+ D2- LOWSP1 RST1 RESUM1 SUSP1 6 HRP1CR-HRP4CR 5 4 3 2 0 1 D1+ Bit 0 D1-
X = Indeterminate
= Unimplemented
Figure 14-4. USB Hub Downstream Port Control Registers (HDP1CR-HDP4CR) PENx -- Downstream Port Enable Control Bit This read/write bit determines whether the enabled or disabled state should be assigned to the downstream port. Setting this bit to 1 enables the port; clearing this bit to 0 disables the port. In the enabled state a full-speed port propagates all downstream signaling;
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 195
Universal Serial Bus Module (USB)
a low-speed port propagates downstream low-speed packet traffic when preceded by the preamble PID. An enabled port propagates all upstream signaling including full-speed and low-speed packets. This bit can be set to 1 by the host request only. It can be cleared either by hardware when a fault condition was detected or by software through the host request. Reset clears this bit. 1 = Downstream port is enabled 0 = Downstream port is disabled LOWSPx -- Full-Speed / Low-Speed Port Control Bit This read/write bit specifies the attached device in the downstream port is low-speed device or full-speed device. Software is responsible to detect the device attachment and whether a device is full or low-speed. Reset clears this bit. 1 = Downstream port is low-speed 0 = Downstream port is full-speed
NOTE:
After a port is enabled, the hub will automatically generate a low-speed keep awake signal to the port every millisecond. RSTx -- Force Reset to the Downstream Port This read/write bit forces a reset signal (SE0 state) onto the USB downstream port data lines. This bit can be set by the host request SetPortFeature (PORT_RESET) only. Software should control the timing of the forced reset signaling downstream for at least 10ms. Reset clears this bit. 1 = Force downstream port data lines to SE0 state 0 = Default RESUMx -- Force Resume to the Downstream Port This read/write bit forces a resume signal (K state) onto the USB downstream port data lines. This bit is set to reflect the resume signal when the software detects the remote resume signal on the data lines of the selective suspend downstream port. Downstream selective resume sequence to a port may also be initiated via the host request ClearPortFeature (PORT_SUSPEND). Software should control the timing of the forced resume signaling downstream for at least 20ms.
Data Sheet 196 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
To indicate the end of the resume, a low-speed EOP signal will be followed when this control bit changes from 1 to 0. Reset clears this bit. 1 = Force downstream port data lines to K state 0 = Default SUSPx -- Downstream Port Selective Suspend Bit This read/write bit forces the downstream port entering the selective suspend mode. This bit can be set by the host request SetPortFeature (PORT_SUSPEND) only. When this bit is set, the hub prevents propagating any bus activity (except the port reset or port resume request or the global reset signal) downstream, and the port can only reflect upstream bus state changes via the endpoint 1 of the hub. The blocking occurs at the next EOF2 point when this bit is set. Reset clears this bit. 1 = Force downstream port enters the selective suspend mode 0 = Default Dx+, Dx- -- Downstream Port Differential Data These read-only bits are the differential data shown on the hub downstream ports. When the SUSPND bit is 0 in the HRPCR register, the data is the latched state at the last EOF2 sample point. When the SUSPND bit is 1, the data reflects the current state on the data line while accessing this register.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 197
Universal Serial Bus Module (USB)
14.6.3 USB SIE Timing Interrupt Register (SIETIR)
Address: $0056 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 SOFF 6 EOF2F 5 EOPF 4 TRANF SOFIE EOF2IE EOPIE TRANIE 3 2 1 Bit 0
= Unimplemented
Figure 14-5. USB SIE Timing Interrupt Register (SIETIR) SOFF -- Start Of Frame Detect Flag This read-only bit is set when a valid SOF PID is detected on the D0+ and D0- lines at the root port. Software must clear this flag by writing a logic 1 to SOFFR bit in the SIETSR register. Reset clears this bit. Writing to SOFF has no effect. 1 = Start Of Frame PID has been detected 0 = Start Of Frame PID has not been detected EOF2F -- Second End Of Frame Point Flag This read-only bit is set when the internal frame timer counts to the bit time that the hub must see upstream traffic terminated near the end of frame. This bit time is defined as 10 bit times from the next Start Of Frame PID. Software must clear this flag by writing a logic 1 to EOF2FR bit in the SIETSR register. Reset clears this bit. Writing to EOF2F has no effect. 1 = Frame timer counts to the EOF2 point 0 = Frame timer does not count to the EOF2 point EOPF -- End of Packet Detect Flag This read-only bit is set when a valid End Of Packet sequence is detected on the D0+ and D0- lines. Software must clear this flag by writing a logic 1 to the EOPFR bit in the SIETSR register. Reset clears this bit. Writing to EOPF has no effect. 1 = End-of-Packet sequence has been detected 0 = End-of-Packet sequence has not been detected
Data Sheet 198 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
TRANF -- Bus Signal Transition Detect Flag This read-only bit is set if there is any bus activity on the upstream or the downstream data lines. Generally, this bit is used to wake up the suspended hub when there is any bus activity occurred. Software must clear this flag by writing a logic 1 to the TRANFR bit in the SIETSR register. Reset clears this bit. Writing to TRANF has no effect. 1 = Signal transition has been detected 0 = Signal transition has not been detected SOFIE -- Start Of Frame Interrupt Enable This read/write bit enables the Start Of Frame to generate a USB interrupt when the SOFF bit becomes set. Reset clears this bit. 1 = USB interrupt enabled for Start Of Frame 0 = USB interrupt disabled for Start Of Frame EOF2IE -- The Second End of Frame Point Interrupt Enable This read/write bit enables the Second End Of Frame to generate a USB interrupt when the EOF2F bit becomes set. Reset clears this bit. 1 = USB interrupt enabled for the Second End Of Frame Point 0 = USB interrupt disabled for the Second End Of Frame Point EOPIE -- End of Packet Detect Interrupt Enable This read/write bit enables the End Of Frame to generate a USB interrupt when the EOPF bit becomes set. Reset clears the bit. 1 = USB interrupt enabled for End-of-Packet sequence detection 0 = USB interrupt disabled for End-of-Packet sequence detection TRANIE -- Bus Signal Transition Detect Interrupt Enable This read/write bit enables the bus signal transition to generate a USB interrupt when the TRANF bit becomes set. Reset clears this bit. 1 = USB interrupt enabled for Bus Signal Transition 0 = USB interrupt disabled for Bus Signal Transition
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 199
Universal Serial Bus Module (USB)
14.6.4 USB SIE Timing Status Register (SIETSR)
Address: $0057 Bit 7 Read: Write: Reset: 0* RSTF 6 0 RSTFR 0 0 5 LOCKF 4 0 LOCKFR 0 3 0 SOFFR 0 2 0 EOF2FR 0 1 0 EOPFR 0 Bit 0 0 TRANFR 0
= Unimplemented * RSTF is reset by a power-on reset (POR) only.
Figure 14-6. USB SIE Timing Status Register (SIETSR) RSTF -- USB Reset Flag This read-only bit is set when a valid USB reset signal state is detected on the D0+ and D0- lines. This bit is cleared by writing a logic 1 to the RSTFR bit or by a MCU power-on reset. 1 = USB reset signal detected on D0+ and D0- 0 = No USB reset detected RSTFR -- Clear Reset Flag Bit Writing a logic 1 to this write-only bit will clear the RSTF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the RSTF bit 0 = No effect LOCKF -- USB Frame Timer Locked This read-only bit is set when the internal frame timer is locked to the host timer. This bit is cleared by writing a logic 1 to the LOCKFR bit. Reset clears this bit. 1 = Internal frame timer is locked to the host timer 0 = Internal frame timer is not locked to the host timer LOCKFR -- Clear Frame Timer Locked Flag Writing a logic 1 to this write-only bit will clear the LOCKF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the LOCKF bit 0 = No effect
Data Sheet 200 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
SOFFR -- Start Of Frame Flag Reset Writing a logic 1 to this write-only bit will clear the SOFF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the SOFF bit 0 = No effect EOF2FR -- The Second End of Frame Point Flag Reset Writing a logic 1 to this write-only bit will clear the EOF2F bit if it is set. Reset clears this bit. 1 = Write 1 to clear the EOF2F bit 0 = No effect EOPFR -- End of Packet Flag Reset Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the EOPF bit 0 = No effect TRANFR -- Bus Signal Transition Flag Reset Writing a logic 1 to this write-only bit will clear the TRANF bit if it is set. Reset clears this bit. 1 = Write 1 to clear TRANF bit 0 = No effect
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 201
Universal Serial Bus Module (USB)
14.6.5 USB Hub Address Register (HADDR)
Address: $0058 Bit 7 Read: USBEN Write: Reset: 0* 0 0 0 0 0 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 6 5 4 3 2 1 Bit 0
* USBEN is reset by a power-on reset (POR) only.
Figure 14-7. USB Hub Address Register (HADDR) USBEN -- USB Module Enable This read/write bit enables and disables the USB module. When USBEN is cleared, the USB module will not respond to any tokens. Power-on reset clears this bit. 1 = USB module enabled 0 = USB module disabled; USB transceiver is also disabled to save power. ADD[6:0] -- USB Hub Function Address These bits specify the address of the hub function. Reset clears these bits.
Data Sheet 202 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
14.6.6 USB Hub Interrupt Register 0 (HIR0)
Address: $0059 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 TXDF 6 RXDF 5 0 4 0 TXDIE RXDIE TXDFR 0 RXDFR 0 3 2 1 0 Bit 0 0
= Unimplemented
Figure 14-8. USB Hub Interrupt Register 0 (HIR0) TXDF -- Hub Endpoint 0 Data Transmit Flag This read-only bit is set after the data stored in hub endpoint 0 transmit buffers have been sent and an ACK handshake packet received from the host. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXDFR bit. To enable the next data packet transmission, TXE must also be set. If TXDF bit is not cleared, a NAK handshake will be returned in the next IN transaction. TXDF generates an interrupt request to CPU if the TXDIE bit is also set. Writing to TXDF has no effect. Reset clears this bit. 1 = Transmit on hub endpoint 0 has occurred 0 = Transmit on hub endpoint 0 has not occurred RXDF -- Hub Endpoint 0 Data Receive Flag This read-only bit is set after the USB hub function has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXDFR bit after all data received have been read. To enable the next data packet reception, RXE must also be set. If RXDF bit is not cleared, a NAK handshake will be returned in the next OUT transaction. RXDF generates an interrupt request to CPU if the RXDIE bit is also set. Writing to RXDF has no effect. Reset clears this bit. 1 = Receive on hub endpoint 0 has occurred 0 = Receive on hub endpoint 0 has not occurred
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 203
Universal Serial Bus Module (USB)
TXDIE -- Hub Endpoint 0 Transmit Interrupt Enable This read/write bit enables the TXDF bit to generate CPU interrupt request when set. Reset clears the TXDIE bit. 1 = TXDF CPU interrupt requests enabled 0 = TXDF CPU interrupt requests disabled RXDIE -- Hub Endpoint 0 Receive Interrupt Enable This read/write bit enables the RXDF bit to generate CPU interrupt request when set. Reset clears the RXDIE bit. 1 = RXDF CPU interrupt requests enabled 0 = RXDF CPU interrupt requests disabled TXDFR -- Hub Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXDF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the TXDF bit 0 = No effect RXDFR -- Hub Endpoint 0 Receive Flag Reset Writing a logic 1 to this write-only bit will clear the RXDF bit if it is set. Reset clears this bit. 1 = Write 1 to clear the RXDF bit 0 = No effect
Data Sheet 204 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
14.6.7 USB Hub Control Register 0 (HCR0)
Address: $005B Bit 7 Read: TSEQ Write: Reset: 0 0 0 0 0 0 0 0 STALL0 TXE RXE TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0 6 5 4 3 2 1 Bit 0
Figure 14-9. USB Hub Control Register 0 (HCR0) TSEQ -- Hub Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at endpoint 0. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next hub endpoint 0 transmit 0 = DATA0 token active for next hub endpoint 0 transmit STALL0 -- Hub Endpoint 0 Force Stall Bit This read/write bit causes hub endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the host. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default TXE -- Hub Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to the hub endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more hub endpoint 0 data packets needs to be transmitted. If this bit is 0 or the TXDF is set, the USB will respond with a NAK handshake to any hub endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready; respond with NAK
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 205
Universal Serial Bus Module (USB)
RXE -- Hub Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB host controller sends an OUT token to the hub endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXDF is set, the USB will respond with a NAK handshake to any hub endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data; respond with NAK TPSIZ[3:0] -- Hub Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for hub endpoint 0. These bits are cleared by reset.
14.6.8 USB Hub Endpoint 1 Control and Data Register (HCDR)
Address: $005C Bit 7 Read: STALL1 Write: Reset: 0 0 0 0 0 0 0 0 PNEW PCHG5 PCHG4 PCHG3 PCHG2 PCHG1 PCHG0 6 5 4 3 2 1 Bit 0
Figure 14-10. USB Hub Endpoint 1 Control and Data Register (HCDR) STALL1 -- Hub Endpoint 1 Force Stall Bit This read/write bit causes hub endpoint 1 to return a STALL handshake when polled by the host. Reset clears this bit. 1 = Send STALL handshake 0 = Default PNEW -- Port New Status Change This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to hub endpoint 1. Software should set this bit when there is a status change on any of the downstream ports, embedded device or hub. It must be cleared by software when there
Data Sheet 206 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Hub Function I/O Registers
is no status change to be reported to the host through endpoint 1. If this bit is 0, a NAK handshake will be returned for next IN token for hub endpoint 1. Reset clears this bit. 1 = Port status change bitmap is ready to be sent 0 = Port status does not change; respond with NAK PCHG5-PCHG0 -- Hub and Port Status Change Bitmap These read/write bits report the status change for the hub, embedded device and the four downstream ports. The status change bitmap is returned to the host through the hub endpoint 1 if the PNEW bit is 1. These bits are cleared by reset.
Bit Name PCHG0 Function Hub status change 1 0 PCHG1 Port 1 status change 1 0 PCHG2 Port 2 status change 1 0 PCHG3 Port 3 status change 1 0 PCHG4 Port 4 status change 1 0 PCHG5 Embedded device status change 1 Port 4 status change detected No status change in embedded device Embedded device status change detected Port 3 status change detected No status change in Port 4 Port 2 status change detected No status change in Port 3 Port 1 status change detected No status change in Port 2 Hub status change detected No status change in Port 1 Value 0 Description No status change in hub
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 207
Universal Serial Bus Module (USB)
14.6.9 USB Hub Status Register (HSR)
Address: $005D Bit 7 Read: Write: Reset: X X X RSEQ 6 SETUP 5 TX1ST 4 0 TX1STR 0 X X X X 3 RPSIZ3 2 RPSIZ2 1 RPSIZ1 Bit 0 RPSIZ0
X = Indeterminate
= Unimplemented
Figure 14-11. USB Hub Status Register (HSR) RSEQ -- Hub Endpoint 0 Receive Sequence Bit This read-only bit indicates the type of data packet last received for hub endpoint 0 (DATA0 or DATA1). 1 = DATA1 token received in last hub endpoint 0 receive 0 = DATA0 token received in last hub endpoint 0 receive SETUP -- Hub SETUP Token Detect Bit This read-only bit indicates that a valid SETUP token has been received. 1 = Last token received for hub endpoint 0 was a SETUP token 0 = Last token received for hub endpoint 0 was not a SETUP token TX1ST -- Hub Transmit First Flag This read-only bit is set if the hub endpoint 0 data transmit flag (TXDF) is set when the USB control logic is setting the hub endpoint 0 data receive flag (RXDF). That is, TXDF is still set at the end of an endpoint 0 reception. This bit allows the software to know that the endpoint 0 transmission happened before the endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT 0 = IN transaction occurred after SETUP/OUT TX1STR -- Clear Hub Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Reset clears this bit. 1 = Write 1 to clear the TX1ST bit 0 = No effect
Data Sheet 208 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
RPSIZ[3:0] -- Hub Endpoint 0 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT or SETUP transaction for hub endpoint 0. These bits are not affected by reset.
14.6.10 USB Hub Endpoint 0 Data Registers (HE0D0-HE0D7)
Address: $0030-$0037 Bit 7 Read: HE0Rx7 Write: HE0Tx7 Reset: 6 HE0Rx6 HE0Tx6 HE0D0-HE0D7 5 HE0Rx5 HE0Tx5 4 HE0Rx4 HE0Tx4 3 HE0Rx3 HE0Tx3 2 HE0Rx2 HE0Tx2 1 HE0Rx1 HE0Tx1 Bit 0 HE0Rx0 HE0Tx0
Indeterminate after reset
Figure 14-12. USB Hub Endpoint 0 Data Registers (HE0D0-HE0D7) HE0Rx[7:0] -- Hub Endpoint 0 Receive Data Buffer These read-only bits are serially loaded with OUT token or SETUP token data directed at hub endpoint 0. The data is received by the D0+ and D0- pins. HE0Tx[7:0] -- Hub Endpoint 0 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at hub endpoint 0.
14.7 Embedded Device Function I/O Registers
The USB embedded device function provides a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the USB embedded device function and the CPU.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 209
Universal Serial Bus Module (USB)
14.7.1 USB Embedded Device Address Register (DADDR)
Address: $0048 Bit 7 Read: DEVEN Write: Reset: 0 0 0 0 0 0 0 0 DADD6 DADD5 DADD4 DADD3 DADD2 DADD1 DADD0 6 5 4 3 2 1 Bit 0
Figure 14-13. USB Embedded Device Address Register (DADDR) DEVEN -- Enable USB Embedded Device These bit enable or disable the embedded device function. It is used together with PEN1-PEN4 to control the enumeration sequence. Reset clears these bits. 1 = USB Embedded Device enabled 0 = USB Embedded Device disabled DADD[6:0] -- USB Embedded Device Function Address These bits specify the address of the embedded device function. Reset clears these bits.
14.7.2 USB Embedded Device Interrupt Register 0 (DIR0)
Address: $0049 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 TXD0F 6 RXD0F 5 0 4 0 TXD0IE RXD0IE TXD0FR 0 RXD0FR 0 3 2 1 0 Bit 0 0
= Unimplemented
Figure 14-14. USB Embedded Device Interrupt Register 0 (DIR0) TXD0F -- Embedded Device Endpoint 0 Data Transmit Flag This read-only bit is set after the data stored in embedded device endpoint 0 transmit buffers have been sent and an ACK handshake packet received from the host. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission,
Data Sheet 210 Universal Serial Bus Module (USB) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction. TXD0F generates an interrupt request to the CPU if the TXD0IE bit is also set. Writing to TXD0F has no effect. Reset clears this bit. 1 = Transmit on embedded device endpoint 0 has occurred 0 = Transmit on embedded device endpoint 0 has not occurred RXD0F -- Embedded Device Endpoint 0 Data Receive Flag This read-only bit is set after the USB embedded device module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD0FR bit after all data received have been read. To enable the next data packet reception, RX0E must also be set. If RXD0F bit is not cleared, a NAK handshake will be returned in the next OUT transaction. RXD0F generates an interrupt request to CPU if the RXD0IE bit is also set. Writing to RXD0F has no effect. Reset clears this bit. 1 = Receive on embedded device endpoint 0 has occurred 0 = Receive on embedded device endpoint 0 has not occurred TXD0IE -- Embedded Device Endpoint 0 Transmit Interrupt Enable This read/write bit enables the TXD0F bit to generate CPU interrupt request when set. Reset clears the TXD0IE bit. 1 = TXD0F CPU interrupt requests enabled 0 = TXD0F CPU interrupt requests disabled RXD0IE -- Embedded Device Endpoint 0 Receive Interrupt Enable This read/write bit enables the RXD0F bit to generate CPU interrupt request when set. Reset clears the RXD0IE bit. 1 = RXD0F CPU interrupt requests enabled 0 = RXD0F CPU interrupt requests disabled TXD0FR -- Embedded Device Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD0F bit if it is set. Reset clears this bit. 1 = Write 1 to clear TXD0F bit 0 = No effect
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 211
Universal Serial Bus Module (USB)
RXD0FR -- Embedded Device Endpoint 0 Receive Flag Reset Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set. Reset clears this bit. 1 = Write 1 to clear RXD0F bit 0 = No effect 14.7.3 USB Embedded Device Interrupt Register 1 (DIR1)
Address: $004A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 TXD1F 6 0 5 0 4 0 TXD1IE TXD1FR 0 0 3 2 0 1 0 Bit 0 0
= Unimplemented
Figure 14-15. USB Embedded Device Interrupt Register 1 (DIR1) TXD1F -- Embedded Device Endpoint 1/2 Data Transmit Flag This read-only bit is shared by endpoint 1 and endpoint 2 of the embedded device. It is set after the data stored in the shared endpoint 1/2 transmit buffer of the embedded device have been sent and an ACK handshake packet received from the host. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E must also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. TXD1F generates an interrupt request to the CPU if the TXD1IE bit is also set. Writing to TXD1F has no effect. Reset clears this bit. 1 = Transmit on endpoint 1 or endpoint 2 of the embedded device has occurred 0 = Transmit on endpoint 1 or endpoint 2 of the embedded device has not occurred TXD1IE -- Embedded Device Endpoint 1/2 Transmit Interrupt Enable This read/write bit enables the TXD1F bit to generate CPU interrupt request when set. Reset clears the TXD1IE bit. 1 = TXD1F CPU interrupt requests enabled 0 = TXD1F CPU interrupt requests disabled
Data Sheet 212 Universal Serial Bus Module (USB) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
TXD1FR -- Embedded Device Endpoint 1/2 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD1F bit if it is set. Reset clears this bit. 1 = Write 1 to clear TXD1F 0 = No effect
14.7.4 USB Embedded Device Control Register 0 (DCR0)
Address: $004B Bit 7 Read: T0SEQ Write: Reset: 0 0 0 0 0 0 0 0 DSTALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 6 5 4 3 2 1 Bit 0
Figure 14-16. USB Embedded Device Control Register 0 (DCR0) T0SEQ -- Embedded Device Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at endpoint 0. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next embedded device endpoint 0 transmit 0 = DATA0 token active for next embedded device endpoint 0 transmit DSTALL0 -- Embedded Device Endpoint 0 Force Stall Bit This read/write bit causes embedded device endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the host. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB)
Data Sheet 213
Universal Serial Bus Module (USB)
TX0E -- Embedded Device Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to the embedded device endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more embedded device endpoint 0 data needs to be transmitted. If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake to any embedded device endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready; respond with NAK RX0E -- Embedded Device Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB host controller sends an OUT token to the embedded device endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake to any embedded device endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data; respond with NAK TP0SIZ[3:0] -- Embedded Device Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for embedded device endpoint 0. These bits are cleared by reset.
Data Sheet 214 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
14.7.5 USB Embedded Device Control Register 1 (DCR1)
Address: $004C Bit 7 Read: T1SEQ Write: Reset: 0 0 0 0 0 0 0 0 ENDADD TX1E 6 5 4 0 TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 3 2 1 Bit 0
= Unimplemented
Figure 14-17. USB Embedded Device Control Register 1 (DCR1) T1SEQ -- Embedded Device Endpoint 1/2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to embedded device endpoint 1 or 2. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next embedded device endpoint 1/2 transmit 0 = DATA0 token active for next embedded device endpoint 1/2 transmit ENDADD -- Endpoint Address Select This read/write bit specifies whether the data inside the DE1D0-DE1D7 registers are used for embedded device endpoint 1 or 2. If all the conditions for a successful endpoint 2 USB response to a host's IN token are satisfied (TXD1F=0, TX1E=1, DSTALL2=0, and ENABLE2=1) except that the ENDADD bit is configured for endpoint 1, the USB responds with a NAK handshake packet. Reset clears this bit. 1 = The data buffers are used for embedded device endpoint 2 0 = The data buffers are used for embedded device endpoint 1 TX1E -- Embedded Device Endpoint 1/2 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to endpoint 1 or endpoint 2 of the embedded device. The appropriate endpoint enable bit, ENABLE1 or ENABLE2 bit in the DCR2 register, should also be set. Software should set the TX1E bit when data is ready to be transmitted.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 215
Universal Serial Bus Module (USB)
It must be cleared by software when no more data needs to be transmitted. If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any endpoint 1 or endpoint 2 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent. 0 = Data is not ready; respond with NAK. TP1SIZ[3:0] -- Embedded Device Endpoint 1/2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for embedded device endpoint 1 or endpoint 2. These bits are cleared by reset.
14.7.6 USB Embedded Device Control Register 2 (DCR2)
Address: $0047 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 ENABLE2 ENABLE1 DSTALL2 DSTALL1 3 2 1 Bit 0
= Unimplemented
Figure 14-18. USB Embedded Device Control Register 2 (DCR2) ENABLE2 -- Embedded Device Endpoint 2 Enable This read/write bit enables embedded device endpoint 2 and allows the USB to respond to IN packets addressed to this endpoint. Reset clears this bit. 1 = Embedded device endpoint 2 is enabled and can respond to an IN token 0 = Embedded device endpoint 2 is disabled ENABLE1 -- Embedded Device Endpoint 1 Enable This read/write bit enables embedded device endpoint 1 and allows the USB to respond to IN packets addressed to this endpoint. Reset clears this bit. 1 = Embedded device endpoint 1 is enabled and can respond to an IN token 0 = Embedded device endpoint 1 is disabled
Data Sheet 216 Universal Serial Bus Module (USB) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
DSTALL2 -- Embedded Device Endpoint 2 Force Stall Bit This read/write bit causes embedded device endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default DSTALL1 -- Embedded Device Endpoint 1 Force Stall Bit This read/write bit causes embedded device endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default 14.7.7 USB Embedded Device Status Register (DSR)
Address: $004D Bit 7 Read: Write: Reset: 0 0 0 DRSEQ 6 DSETUP 5 DTX1ST 4 0 DTX1STR 0 0 0 0 0 3 RP0SIZ3 2 RP0SIZ2 1 RP0SIZ1 Bit 0 RP0SIZ0
= Unimplemented
Figure 14-19. USB Embedded Device Status Register (DSR) DRSEQ -- Embedded Device Endpoint 0 Receive Sequence Bit This read-only bit indicates the type of data packet last received for embedded device endpoint 0 (DATA0 or DATA1). 1 = DATA1 token received in last embedded device endpoint 0 receive 0 = DATA0 token received in last embedded device endpoint 0 receive DSETUP -- Embedded Device SETUP Token Detect Bit This read-only bit indicates that a valid SETUP token has been received. 1 = Last token received for endpoint 0 was a SETUP token 0 = Last token received for endpoint 0 was not a SETUP token
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 217
Universal Serial Bus Module (USB)
DTX1ST -- Embedded Device Transmit First Flag This read-only bit is set if the embedded device endpoint 0 data transmit flag (TXD0F) is set when the USB control logic is setting the embedded device endpoint 0 data receive flag (RXD0F). That is, TXD0F is still set at the end of an endpoint 0 reception. This bit allows the software to know that the endpoint 0 transmission happened before the endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT 0 = IN transaction occurred after SETUP/OUT DTX1STR -- Clear Transmit First Flag Writing a logic 1 to this write-only bit will clear the DTX1ST bit if it is set. Reset clears this bit. 1 = Write 1 to clear DTX1ST bit 0 = No effect RP0SIZ[3:0] -- Embedded Device Endpoint 0 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT or SETUP transaction for embedded device endpoint 0. These bits are not affected by reset.
Data Sheet 218 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Universal Serial Bus Module (USB) Embedded Device Function I/O Registers
14.7.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7)
Address: $0020-$0027 Bit 7 Read: DE0Rx7 Write: DE0Tx7 Reset: 6 DE0Rx6 DE0Tx6 DE0D0-DE0D7 5 DE0Rx5 DE0Tx5 4 DE0Rx4 DE0Tx4 3 DE0Rx3 DE0Tx3 2 DE0Rx2 DE0Tx2 1 DE0Rx1 DE0Tx1 Bit 0 DE0Rx0 DE0Tx0
Indeterminate after reset
Figure 14-20. USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7) DE0Rx[7:0] -- Embedded Device Endpoint 0 Receive Data Buffer These read-only bits are serially loaded with OUT token or SETUP token data directed at embedded device endpoint 0. The data is received by the D0+ and D0- pins. DE0Tx[7:0] -- Embedded Device Endpoint 0 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at embedded device endpoint 0. 14.7.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7)
Address: $0028-$002F Bit 7 Read: Write: DE1Tx7 Reset: DE1Tx6 DE1Tx5 DE1Tx4 DE1Tx3 DE1Tx2 DE1Tx1 DE1Tx0 6 DE1D0-DE1D7 5 4 3 2 1 Bit 0
Indeterminate after reset
Figure 14-21. USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7) DE1Tx[7:0] -- Embedded Device Endpoint 1/ Endpoint 2 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 1 or endpoint 2 of the embedded device. These buffers are shared by embedded device endpoints 1 and 2 and depend on proper configuration of the ENDADD bit.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Universal Serial Bus Module (USB) Data Sheet 219
Universal Serial Bus Module (USB)
Data Sheet 220 Universal Serial Bus Module (USB)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 15. Multi-Master IIC Interface (MMIIC)
15.1 Contents
15.2 15.3 15.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . 224 15.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . 225 15.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . . 226 15.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . 228 15.5.5 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . 230 15.5.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . 231 15.6 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.2 Introduction
This Multi-master IIC (MMIIC) Interface is designed for internal serial communication between the MCU and other IIC devices. A hardware circuit generates "start" and "stop" signal, while byte by byte data transfer is interrupt driven by the software algorithm. Therefore, it can greatly help the software in dealing with other devices to have higher system efficiency in a typical digital monitor system. This module not only can be applied in internal communications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 221
Multi-Master IIC Interface (MMIIC)
This Multi-master IIC module uses the IICSCL clock line and the IICSDA data line to communicate with external DDC host or IIC interface. These two pins are shared with port pins PTD6 and PTD7 respectively. The outputs of IICSDA and IICSCL pins are open-drain type -- no clamping diode is connected between the pin and internal VDD. The maximum data rate typically is 750k-bps. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF.
15.3 Features
* * * * * * * * * * Compatibility with multi-master IIC bus standard Software controllable acknowledge bit generation Interrupt driven byte by byte data transfer Calling address identification interrupt Auto detection of R/W bit and switching of transmit or receive mode Detection of START, repeated START, and STOP signals Auto generation of START and STOP condition in master mode Arbitration loss detection and No-ACK awareness in master mode 8 selectable baud rate master clocks Automatic recognition of the received acknowledge bit
15.4 I/O Pins
The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O pins are listed in Table 15-1. The generic pin name appear in the text that follows. Table 15-1. Pin Name Conventions
MMIIC Generic Pin Names: SDA SCL Full MCU Pin Names: PTD7/IICSDA PTD6/IICSCL Pin Selected for IIC Function By: IICDATE bit in PDCR ($0069) IICSCLE bit in PDCR ($0069)
Data Sheet 222 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers
Addr. $006A
Register Name
Bit 7
6
5 MMBB 0 MMAD5 1 0 0
4 MMAST 0 MMAD4 0 0 0
3 MMRW 0 MMAD3 0 MMTXAK 0
2 MMBR2 0 MMAD2 0 0 0 0 0 MMTD2 1 MMRD2
1 MMBR1 0
Bit 0 MMBR0 0
Read: MMALIF MMNAKIF Multi-Master IIC Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 Read: Multi-Master IIC Address MMAD7 Register Write: (MMADR) Reset: 1 Read: Multi-Master IIC Control Register Write: (MMCR) Reset: MMEN 0 MMAD6 0 MMIEN 0 MMTXIF 0 0 MMTD6 1 MMRD6
$006B
MMAD1 MMEXTAD 0 0 0 0 0 0
$006C
$006D
Multi-Master IIC Read: MMRXIF Status Register Write: 0 (MMSR) Reset: 0 Multi-Master IIC Read: MMTD7 Data Transmit Register Write: (MMDTR) Reset: 1 Multi-Master IIC Read: MMRD7 Data Receive Register Write: (MMDRR) Reset: 0
MMATCH MMSRW MMRXAK 0 MMTD5 1 MMRD5 0 MMTD4 1 MMRD4 1 MMTD3 1 MMRD3
MMTXBE MMRXBF 1 MMTD1 1 MMRD1 0 MMTD0 1 MMRD0
$006E
$006F
0
0
0
0
0
0
0
= Unimplemented
Figure 15-1. MMIIC I/O Register Summary
15.5 Multi-Master IIC Registers
Six registers are associated with the Multi-master IIC module, they are outlined in the following sections.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 223
Multi-Master IIC Interface (MMIIC)
15.5.1 Multi-Master IIC Address Register (MMADR)
Address: $006B Bit 7 Read: MMAD7 Write: Reset: 1 0 1 0 0 0 0 0 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 6 5 4 3 2 1 Bit 0
Figure 15-2. Multi-Master IIC Address Register (MMADR) MMAD[7:1] -- Multi-Master Address These seven bits can be the MMIIC interface's own specific slave address in slave mode or the calling address when in master mode. Software must update it as the calling address while entering the master mode and restore its own slave address after the master mode is relinquished. Reset sets a default value of $A0. MMEXTAD -- Multi-Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will acknowledge the general call address $00 and the matched 4-bit address, MMAD[7:4]. Reset clears this bit. For example, when MMADR is configured as:
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 1 1 0 1 X X X 1
The MMIIC module will respond to the calling address:
Bit 7 1 6 1 5 0 4 1 3 X 2 X Bit 1 X
or the general calling address:
0 0 0 0 0 0 0
where X = don't care; bit 0 of the calling address is the MMRW bit from the calling master. 1 = MMIIC responds to address $00 and $MMAD[7:4] 0 = MMIIC responds to address $MMAD[7:1]
Data Sheet 224 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers
15.5.2 Multi-Master IIC Control Register (MMCR)
Address: $006C Bit 7 Read: MMEN Write: Reset: 0 0 0 0 0 0 0 0 MMIEN 6 5 0 4 0 MMTXAK 3 2 0 1 0 Bit 0 0
= Unimplemented
Figure 15-3. Multi-Master IIC Control Register (MMCR) MMEN -- Multi-Master IIC Enable This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags will restore to its poweron default states. Reset clears this bit. 1 = MMIIC module enabled 0 = MMIIC module disabled MMIEN -- Multi-Master IIC Interrupt Enable When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF flags are enabled to generate an interrupt request to the CPU. When MMIEN is cleared, the these flags are prevented from generating an interrupt request. Reset clears this bit. 1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU 0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not generate interrupt request to CPU MMTXAK -- Transmit Acknowledge Enable This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. 1 = MMIIC does not send acknowledge signals at 9th clock bit 0 = MMIIC sends acknowledge signal at 9th clock bit
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 225
Multi-Master IIC Interface (MMIIC)
15.5.3 Multi-Master IIC Master Control Register (MIMCR)
Address: $006A Bit 7 6 5 MMBB MMAST Write: Reset: 0 0 0 0 0 0 0 0 0 0 MMRW MMBR2 MMBR1 MMBR0 4 3 2 1 Bit 0
Read: MMALIF MMNAKIF
Figure 15-4. Multi-Master IIC Master Control Register (MIMCR) MMALIF -- Multi-Master Arbitration Lost Interrupt Flag This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA line in master mode - an arbitration loss. This bit generates an interrupt request to the CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = Lost arbitration in master mode 0 = No arbitration lost MMNAKIF -- No Acknowledge Interrupt Flag This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = No acknowledge bit detected 0 = Acknowledge bit detected MMBB -- Bus Busy Flag This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the MMIIC is disabled. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or MMIIC is disabled
Data Sheet 226 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers
MMAST -- Master Control Bit This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR. When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module generates the stop condition to the lines after the current byte is transmitted. If an arbitration loss occurs (MMALIF = 1), the module reverts to slave mode by clearing MMAST, and releasing SDA and SCL lines immediately. This bit is cleared by writing "0" to it or by reset. 1 = Master mode operation 0 = Slave mode operation MMRW -- Master Read/Write This bit will be transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit. 1 = Master mode receive 0 = Master mode transmit MMBR2-MMBR0 -- Baud Rate Select These three bits select one of eight clock rates as the master clock when the module is in master mode. Since this master clock is derived the CPU bus clock, the user program should not execute the WAIT instruction when the MMIIC module in master mode. This will cause the SDA and SCL lines to hang, as the WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared upon reset. (See Table 15-2 . Baud Rate Select.)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 227
Multi-Master IIC Interface (MMIIC)
Table 15-2. Baud Rate Select
MMBR2 0 0 0 0 1 1 1 1 MMBR1 0 0 1 1 0 0 1 1 MMBR0 0 1 0 1 0 1 0 1 Baud Rate 750k 375k 187.5k 93.75k 46.875k 23.437k 11.719k 5.859k
NOTE: CPU bus clock is external clock / 4 = 6MHz
15.5.4 Multi-Master IIC Status Register (MMSR)
Address: $006D Bit 7 Read: MMRXIF Write: Reset: 0 0 6 MMTXIF 0 0 0 0 1 0 1 0 5 4 3 2 0 1 Bit 0
MMATCH MMSRW MMRXAK
MMTXBE MMRXBF
= Unimplemented
Figure 15-5. Multi-Master IIC Status Register (MMSR) MMRXIF -- Multi-Master IIC Receive Interrupt Flag This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset; or when the MMEN = 0. 1 = New data in data receive register (MMDRR) 0 = No data received
Data Sheet 228 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers
MMTXIF -- Multi-Master Transmit Interrupt Flag This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0. 1 = Data transfer completed 0 = Data transfer in progress MMATCH -- Multi-Master Address Match This flag is set when the received data in the data receive register (MMDRR) is an calling address which matches with the address or its extended addresses (MMEXTAD=1) specified in the MMADR register. 1 = Received address matches MMADR 0 = Received address does not match MMSRW -- Multi-Master Slave Read/Write This bit indicates the data direction when the module is in slave mode. It is updated after the calling address is received from a master device. MMSRW = 1 when the calling master is reading data from the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive mode). 1 = Slave mode transmit 0 = Slave mode receive MMRXAK -- Multi-Master Receive Acknowledge When this bit is cleared, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has been detected at the 9th clock; the module will release the SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. 1 = No acknowledge signal received at 9th clock bit 0 = Acknowledge signal received at 9th clock bit
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 229
Multi-Master IIC Interface (MMIIC)
MMTXBE -- Multi-Master Transmit Buffer Empty This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full MMRXBF -- Multi-Master Receive Buffer Full This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data from the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer of data from the input circuit to the MMDRR. Reset clears this bit. 1 = Data receive register full 0 = Data receive register empty 15.5.5 Multi-Master IIC Data Transmit Register (MMDTR)
Address: $006E Bit 7 Read: MMTD7 Write: Reset: 1 1 1 1 1 1 1 1 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0 6 5 4 3 2 1 Bit 0
Figure 15-6. Multi-Master IIC Data Transmit Register (MMDTR) When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether module is in master or slave mode. In slave mode, the data in MMDTR will be transferred to the output circuit when: * * the module detects a matched calling address (MMATCH = 1), with the calling master requesting data (MMSRW = 1); or the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
Data Sheet 230 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers
If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (MMTXBE = 0). In master mode, the data in MMDTR will be transferred to the output circuit when: * the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
*
If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (MMTXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 15-8.
15.5.6 Multi-Master IIC Data Receive Register (MMDRR)
Address : $006F Bit 7 6 5 4 3 2 1 Bit 0
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Write: Reset: 0 0 0 0 0 0 0 0
= Unimplemente d
Figure 15-7. Multi-Master IIC Data Receive Register (MMDRR) When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether module is in master or slave mode.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 231
Multi-Master IIC Interface (MMIIC)
In slave mode, the data in MMDRR is: * * the calling address from the master when the address match flag is set (MMATCH = 1); or the last data received when MMATCH = 0.
In master mode, the data in the MMDRR is: * the last data received.
When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF interrupt flag is set, indicating that new data is available in MMDRR. The sequence of events for slave receive and master receive are illustrated in Figure 15-8.
15.6 Programming Considerations
When the MMIIC module detects an arbitration loss in master mode, it will release both SDA and SCL lines immediately. But if there are no further STOP conditions detected, the module will hang up. Therefore, it is recommended to have time-out software to recover from such ill condition. The software can start the time-out counter by looking at the MMBB (Bus Busy) flag in the MIMCR and reset the counter on the completion of one byte transmission. If a time-out occur, software can clear the MMEN bit (disable MMIIC module) to release the bus, and hence clearing the MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due to a no STOP condition received. The MMIIC can resume operation again by setting the MMEN bit.
Data Sheet 232 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Multi-Master IIC Interface (MMIIC) Programming Considerations
(a) Master Transmit Mode
START Address 0 ACK TX Data1 ACK TX DataN NAK STOP
MMTXBE=0 MMRW=0 MMAST=1 Data1 MMDTR
MMTXBE=1 MMTXIF=1 Data2 MMDTR
MMTXBE=1 MMTXIF=1 Data3 MMDTR
MMTXBE=1 MMNAKIF=1 MMTXIF=1 MMAST=0 DataN+2 MMDTR MMTXBE=0
(b) Master Receive Mode
START Address 1 ACK RX Data1 ACK RX DataN NAK STOP
MMRXBF=0 MMRW=1 MMAST=1 MMTXBE=0 (dummy data MMDTR)
Data1 MMDRR MMRXIF=1 MMRXBF=1
DataN MMDRR MMNAKIF=1 MMRXIF=1 MMAST=0 MMRXBF=1
(c) Slave Transmit Mode
START Address 1 ACK TX Data1 ACK TX DataN NAK STOP
MMTXBE=1 MMRXBF=0
MMRXIF=1 MMRXBF=1 MMATCH=1 MMSRW=1 Data1 MMDTR
MMTXBE=1 MMTXIF=1 Data2 MMDTR
MMTXBE=1 MMNAKIF=1 MMTXIF=1 MMTXBE=0 DataN+2 MMDTR
(d) Slave Receive Mode
START Address 0 ACK RX Data1 ACK RX DataN NAK STOP
MMTXBE=0 MMRXBF=0
MMRXIF=1 MMRXBF=1 MMATCH=1 MMSRW=0
Data1 MMDRR MMRXIF=1 MMRXBF=1
DataN MMDRR MMRXIF=1 MMRXBF=1
KEY: shaded data packets indicate a transmit by the MCU's MMIIC module
Figure 15-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Multi-Master IIC Interface (MMIIC)
Data Sheet 233
Multi-Master IIC Interface (MMIIC)
Data Sheet 234 Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 16. DDC12AB Interface
16.1 Contents
16.2 16.3 16.4 16.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
16.6 DDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6.1 DDC Address Register (DDCADR) . . . . . . . . . . . . . . . . . . 238 16.6.2 DDC2 Address Register (DDC2ADR) . . . . . . . . . . . . . . . . 239 16.6.3 DDC Control Register (DDCCR) . . . . . . . . . . . . . . . . . . . . 240 16.6.4 DDC Master Control Register (DDCMCR) . . . . . . . . . . . . . 241 16.6.5 DDC Status Register (DDCSR) . . . . . . . . . . . . . . . . . . . . . 244 16.6.6 DDC Data Transmit Register (DDCDTR) . . . . . . . . . . . . . . 246 16.6.7 DDC Data Receive Register (DDCDRR) . . . . . . . . . . . . . . 247 16.7 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 248
16.2 Introduction
This DDC12AB Interface module is used by the digital monitor to show its identification information to the video controller. It contains DDC1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master IIC bus protocol to support DDC2AB interface. This module not only can be applied in internal communications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface Data Sheet 235
DDC12AB Interface
This DDC12AB module uses the DDCSCL clock line and the DDCSDA data line to communicate with external DDC host or IIC interface. These two pins are shared with port pins PTD4 and PTD5 respectively. The outputs of DDCSDA and DDCSCL pins are open-drain type -- no clamping diode is connected between the pin and internal VDD. The maximum data rate typically is 100k-bps. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF.
16.3 Features
* * * * * * * * * * * DDC1 hardware Compatibility with multi-master IIC bus standard Software controllable acknowledge bit generation Interrupt driven byte by byte data transfer Calling address identification interrupt Auto detection of R/W bit and switching of transmit or receive mode Detection of START, repeated START, and STOP signals Auto generation of START and STOP condition in master mode Arbitration loss detection and No-ACK awareness in master mode 8 selectable baud rate master clocks Automatic recognition of the received acknowledge bit
16.4 I/O Pins
The DDC12AB module uses two I/O pins, shared with standard port I/O pins. The full name of the DDC12AB I/O pins are listed in Table 16-1. The generic pin name appear in the text that follows. Table 16-1. Pin Name Conventions
DDC12AB Generic Pin Names: SDA SCL Data Sheet 236 DDC12AB Interface Full MCU Pin Names: PTD5/DDCSDA PTD4/DDCSCL Pin Selected for DDC Function By: DDCDATE bit in PDCR ($0069) DDCSCLE bit in PDCR ($0069) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface I/O Pins
Addr.
Register Name DDC Master Control Register (DDCMCR) Read: Write: Reset: Read:
Bit 7 ALIF 0 0 DAD7 Write: Reset: Read: 1 DEN Write: Reset: Read: 0 RXIF 0 0 DTD7 Write: Reset: Read: Write: Reset: Read: 0 D2AD7 Write: Reset: 0 1 DRD7
6 NAKIF 0 0 DAD6 0 DIEN 0 TXIF 0 0 DTD6 1 DRD6
5 BB
4 MAST
3 MRW 0 DAD3 0 TXAK
2 BR2 0 DAD2 0 SCLIEN 0 SCLIF 0
1 BR1 0 DAD1 0 DDC1EN 0 TXBE
Bit 0 BR0 0 EXTAD 0 0
$0016
0 DAD5 1 0
0 DAD4 0 0
$0017
DDC Address Register (DDCADR)
$0018
DDC Control Register (DDCCR)
0 MATCH
0 SRW
0 RXAK
0 RXBF
$0019
DDC Status Register (DDCSR)
Write: Reset:
0 DTD5 1 DRD5
0 DTD4 1 DRD4
1 DTD3 1 DRD3
0 DTD2 1 DRD2
1 DTD1 1 DRD1
0 DTD0 1 DRD0
$001A
DDC Data Transmit Register (DDCDTR) DDC Data Receive Register (DDCDRR)
Read:
$001B
0 D2AD6 0
0 D2AD5 0
0 D2AD4 0
0 D2AD3 0
0 D2AD2 0
0 D2AD1 0
0 0
$001C
DDC2 Address Register (DDC2ADR)
0
= Unimplemented
Figure 16-1. DDC I/O Register Summary
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 237
DDC12AB Interface 16.5 DDC Protocols
In DDC1 protocol communication, the module is in transmit mode. The data written to the transmit register is continuously clocked out to the SDA line by the rising edge of the Vsync input signal. During DDC1 communication, a falling transition on the SCL line can be detected to generate an interrupt to the CPU for mode switching. In DDC2AB protocol communication, the module can be either in transmit mode or in receive mode, controlled by the calling master. In DDC2 protocol communication, the module will act as a standard IIC module, able to act as a master or a slave device.
16.6 DDC Registers
Seven registers are associated with the DDC module, they are outlined in the following sections.
16.6.1 DDC Address Register (DDCADR)
Address: $0017 Bit 7 Read: DAD7 Write: Reset: 1 0 1 0 0 0 0 0 DAD6 DAD5 DAD4 DAD3 DAD2 DAD1 EXTAD 6 5 4 3 2 1 Bit 0
Figure 16-2. DDC Address Register (DDCADR) DAD[7:1] -- DDC Address These seven bits can be the DDC2 interface's own specific slave address in slave mode or the calling address when in master mode. Software must update it as the calling address while entering the master mode and restore its own slave address after the master mode is relinquished. Reset sets a default value of $A0.
Data Sheet 238 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface DDC Registers
EXTAD -- DDC Expanded Address This bit is set to expand the address of the DDC in slave mode. When set, the DDC will acknowledge the general call address $00 and the matched 4-bit address, DAD[7:4]. Reset clears this bit. For example, when DDCADR is configured as:
DAD7 1 DAD6 1 DAD5 0 DAD4 1 DAD3 X DAD2 X DAD1 X EXTAD 1
The DDC module will respond to the calling address:
Bit 7 1 6 1 5 0 4 1 3 X 2 X Bit 1 X
or the general calling address:
0 0 0 0 0 0 0
where X = don't care; bit 0 of the calling address is the MRW bit from the calling master. 1 = DDC responds to address $00 and $DAD[7:4] 0 = DDC responds to address $DAD[7:1]
16.6.2 DDC2 Address Register (DDC2ADR)
Address: $001C Bit 7 Read: D2AD7 Write: Reset: 0 0 0 0 0 0 0 0 D2AD6 D2AD5 D2AD4 D2AD3 D2AD2 D2AD1 6 5 4 3 2 1 Bit 0 0
Figure 16-3. DDC2 Address Register (DDC2ADR) D2AD[7:1] -- DDC2 Address These seven bits represent the second slave address for the DDC2BI protocol. D2AD[7:1] should be set to the same value as DAD[7:1] in DDCADR if user application do not use DDC2BI. Reset clears all bits this register.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface Data Sheet 239
DDC12AB Interface
16.6.3 DDC Control Register (DDCCR)
Address: $0018 Bit 7 Read: DEN Write: Reset: 0 0 0 0 0 0 0 0 DIEN 6 5 0 4 0 TXAK SCLIEN DDC1EN 3 2 1 Bit 0 0
= Unimplemented
Figure 16-4. DDC Control Register (DDCCR) DEN -- DDC Enable This bit is set to enable the DDC module. When DEN = 0, module is disabled and all flags will restore to its power-on default states. Reset clears this bit. 1 = DDC module enabled 0 = DDC module disabled DIEN -- DDC Interrupt Enable When this bit is set, the TXIF, RXIF, ALIF, and NAKIF flags are enabled to generate an interrupt request to the CPU. When DIEN is cleared, the these flags are prevented from generating an interrupt request. Reset clears this bit. 1 = TXIF, RXIF, ALIF, and/or NAKIF bit set will generate interrupt request to CPU 0 = TXIF, RXIF, ALIF, and/or NAKIF bit set will not generate interrupt request to CPU TXAK -- Transmit Acknowledge Enable This bit is set to disable the DDC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When TXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. 1 = DDC does not send acknowledge signals at 9th clock bit 0 = DDC sends acknowledge signal at 9th clock bit
Data Sheet 240 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface DDC Registers
SCLIEN -- SCL Interrupt Enable When this bit is set, the SCLIF flag is enabled to generate an interrupt request to the CPU. When SCLIEN is cleared, SCLIF is prevented from generating an interrupt request. Reset clears this bit. 1 = SCLIF bit set will generate interrupt request to CPU 0 = SCLIF bit set will not generate interrupt request to CPU DDC1EN -- DDC1 Protocol Enable This bit is set to enable DDC1 protocol. The DDC1 protocol will use the Vsync input (from sync processor) as the master clock input to the DDC module. Vsync rising-edge will continuously clock out the data to the output circuit. No calling address comparison is performed. The SRW bit in DDC status register (DDCSR) will always read as "1". Reset clears this bit. 1 = DDC1 protocol enabled 0 = DDC1 protocol disabled
16.6.4 DDC Master Control Register (DDCMCR)
Address: $0016 Bit 7 Read: Write: Reset: ALIF 0 0 6 NAKIF 0 0 0 0 0 0 0 0 5 BB MAST MRW BR2 BR1 BR0 4 3 2 1 Bit 0
Figure 16-5. DDC Master Control Register (DDCMCR) ALIF -- DDC Arbitration Lost Interrupt Flag This flag is set when software attempt to set MAST but the BB has been set by detecting the start condition on the lines or when the DDC is transmitting a "1" to SDA line but detected a "0" from SDA line in master mode - an arbitration loss. This bit generates an interrupt request to the CPU if the DIEN bit in DDCCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = Lost arbitration in master mode 0 = No arbitration lost
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 241
DDC12AB Interface
NAKIF -- No Acknowledge Interrupt Flag This flag is only set in master mode (MAST = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. This flag also clears MAST. NAKIF generates an interrupt request to CPU if the DIEN bit in DDCCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = No acknowledge bit detected 0 = Acknowledge bit detected BB -- Bus Busy Flag This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the DDC is disabled. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or DDC is disabled MAST -- Master Control Bit This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition to the SDA and SCL lines, followed by sending the calling address stored in DDCADR. When the MAST bit is cleared by NAKIF set (no acknowledge) or by software, the module generates the stop condition to the lines after the current byte is transmitted. If an arbitration loss occurs (ALIF = 1), the module reverts to slave mode by clearing MAST, and releasing SDA and SCL lines immediately. This bit is cleared by writing "0" to it or by reset. 1 = Master mode operation 0 = Slave mode operation MRW -- Master Read/Write This bit will be transmitted out as bit 0 of the calling address when the module sets the MAST bit to enter master mode. The MRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit. 1 = Master mode receive 0 = Master mode transmit
Data Sheet 242 DDC12AB Interface MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface DDC Registers
BR2-BR0 -- Baud Rate Select These three bits select one of eight clock rates as the master clock when the module is in master mode. Since this master clock is derived the CPU bus clock, the user program should not execute the WAIT instruction when the DDC module in master mode. This will cause the SDA and SCL lines to hang, as the WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared upon reset. (See Table 16-2 . Baud Rate Select.) Table 16-2. Baud Rate Select
BR2 0 0 0 0 1 1 1 1 BR1 0 0 1 1 0 0 1 1 BR0 0 1 0 1 0 1 0 1 Baud Rate 100k 50k 25k 12.5k 6.25k 3.125k 1.56k 0.78k
NOTE: CPU bus clock is external clock / 4 = 6MHz
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 243
DDC12AB Interface
16.6.5 DDC Status Register (DDCSR)
Address: $0019 Bit 7 Read: Write: Reset: RXIF 0 0 6 TXIF 0 0 0 0 1 5 MATCH 4 SRW 3 RXAK 2 SCLIF 0 0 1 0 1 TXBE Bit 0 RXBF
= Unimplemented
Figure 16-6. DDC Status Register (DDCSR) RXIF -- DDC Receive Interrupt Flag This flag is set after the data receive register (DDCDRR) is loaded with a new received data. Once the DDCDRR is loaded with received data, no more received data can be loaded to the DDCDRR until the CPU reads the data from the DDCDRR to clear RXBF flag. RXIF generates an interrupt request to CPU if the DIEN bit in DDCCR is also set. This bit is cleared by writing "0" to it or by reset; or when the DEN = 0. 1 = New data in data receive register (DDCDRR) 0 = No data received TXIF -- DDC Transmit Interrupt Flag This flag is set when data in the data transmit register (DDCDTR) is downloaded to the output circuit, and that new data can be written to the DDCDTR. TXIF generates an interrupt request to CPU if the DIEN bit in DDCCR is also set. This bit is cleared by writing "0" to it or when the DEN = 0. 1 = Data transfer completed 0 = Data transfer in progress MATCH -- DDC Address Match This flag is set when the received data in the data receive register (DDCDRR) is a calling address which matches with the address or its extended addresses (EXTAD=1) specified in the DDCADR register. 1 = Received address matches DDCADR 0 = Received address does not match
Data Sheet 244 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface DDC Registers
SRW -- DDC Slave Read/Write This bit indicates the data direction when the module is in slave mode. It is updated after the calling address is received from a master device. SRW = 1 when the calling master is reading data from the module (slave transmit mode). SRW = 0 when the master is writing data to the module (receive mode). 1 = Slave mode transmit 0 = Slave mode receive RXAK -- DDC Receive Acknowledge When this bit is cleared, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. When RXAK is set, it indicates no acknowledge signal has been detected at the 9th clock; the module will release the SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. 1 = No acknowledge signal received at 9th clock bit 0 = Acknowledge signal received at 9th clock bit SCLIF -- SCL Interrupt Flag This flag is set when a falling edge is detected on the SCL line, only if DDC1EN bit is set. SCLIF generates an interrupt request to CPU if the SCLIEN bit in DDCCR is also set. SCLIF is cleared by writing "0" to it or when the DCC1EN = 0, or DEN = 0. Reset clears this bit. 1 = Falling edge detected on SCL line 0 = No falling edge detected on SCL line TXBE -- DDC Transmit Buffer Empty This flag indicates the status of the data transmit register (DDCDTR). When the CPU writes the data to the DDCDTR, the TXBE flag will be cleared. TXBE is set when DDCDTR is emptied by a transfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 245
DDC12AB Interface
RXBF -- DDC Receive Buffer Full This flag indicates the status of the data receive register (DDCDRR). When the CPU reads the data from the DDCDRR, the RXBF flag will be cleared. RXBF is set when DDCDRR is full by a transfer of data from the input circuit to the DDCDRR. Reset clears this bit. 1 = Data receive register full 0 = Data receive register empty 16.6.6 DDC Data Transmit Register (DDCDTR)
Address: $001A Bit 7 Read: DTD7 Write: Reset: 1 1 1 1 1 1 1 1 DTD6 DTD5 DTD4 DTD3 DTD2 DTD1 DTD0 6 5 4 3 2 1 Bit 0
Figure 16-7. DDC Data Transmit Register (DDCDTR) When the DDC module is enabled, DEN = 1, data written into this register depends on whether module is in master or slave mode. In slave mode, the data in DDCDTR will be transferred to the output circuit when: * * the module detects a matched calling address (MATCH = 1), with the calling master requesting data (SRW = 1); or the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit, indicated by a received acknowledge bit (RXAK = 0).
If the calling master does not return an acknowledge bit (RXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the DDCDTR will not be transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (TXBE = 0). In master mode, the data in DDCDTR will be transferred to the output circuit when:
Data Sheet 246 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface DDC Registers
*
the module receives an acknowledge bit (RXAK = 0), after setting master transmit mode (MRW = 0), and the calling address has been transmitted; or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (RXAK = 0).
*
If the slave does not return an acknowledge bit (RXAK = 1), the master will generate a "stop" or "repeated start" condition. The data in the DDCDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (TXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 16-9.
16.6.7 DDC Data Receive Register (DDCDRR)
Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 DRD7 6 DRD6 5 DRD5 4 DRD4 3 DRD3 2 DRD2 1 DRD1 Bit 0 DRD0
= Unimplemented
Figure 16-8. DDC Data Receive Register (DDCDRR) When the DDC module is enabled, DEN = 1, data in this read-only register depends on whether module is in master or slave mode. In slave mode, the data in DDCDRR is: * * the calling address from the master when the address match flag is set (MATCH = 1); or the last data received when MATCH = 0.
In master mode, the data in the DDCDRR is: * the last data received.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 247
DDC12AB Interface
When the DDCDRR is read by the CPU, the receive buffer full flag is cleared (RXBF = 0), and the next received data is loaded to the DDCDRR. Each time when new data is loaded to the DDCDRR, the RXIF interrupt flag is set, indicating that new data is available in DDCDRR. The sequence of events for slave receive and master receive are illustrated in Figure 16-9.
16.7 Programming Considerations
When the DDC module detects an arbitration loss in master mode, it will release both SDA and SCL lines immediately. But if there are no further STOP conditions detected, the module will hang up. Therefore, it is recommended to have time-out software to recover from such ill condition. The software can start the time-out counter by looking at the BB (Bus Busy) flag in the DDCMCR and reset the counter on the completion of one byte transmission. If a time-out occur, software can clear the DEN bit (disable DDC module) to release the bus, and hence clearing the BB flag. This is the only way to clear the BB flag by software if the module hangs up due to a no STOP condition received. The DDC can resume operation again by setting the DEN bit.
Data Sheet 248 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
DDC12AB Interface Programming Considerations
(a) Master Transmit Mode
START Address 0 ACK TX Data1 ACK TX DataN NAK STOP
TXBE=0 MRW=0 MAST=1 Data1 DDCDTR
TXBE=1 TXIF=1 Data2 DDCDTR
TXBE=1 TXIF=1 Data3 DDCDTR
TXBE=1 NAKIF=1 TXIF=1 MAST=0 DataN+2 DDCDTR TXBE=0
(b) Master Receive Mode
START Address 1 ACK RX Data1 ACK RX DataN NAK STOP
RXBF=0 MRW=1 MAST=1 TXBE=0 (dummy data DDCDTR)
Data1 DDCDRR RXIF=1 RXBF=1
DataN DDCDRR RXIF=1 RXBF=1
NAKIF=1 MAST=0
(c) Slave Transmit Mode
START Address 1 ACK TX Data1 ACK TX DataN NAK STOP
TXBE=1 RXBF=0
RXIF=1 TXBE=1 RXBF=1 TXIF=1 MATCH=1 Data2 DDCDTR SRW=1 Data1 DDCDTR
TXBE=1 TXIF=1 DataN+2 DDCDTR
NAKIF=1 TXBE=0
(d) Slave Receive Mode
START Address 0 ACK RX Data1 ACK RX DataN NAK STOP
TXBE=0 RXBF=0
RXIF=1 RXBF=1 MATCH=1 SRW=0
Data1 DDCDRR RXIF=1 RXBF=1
DataN DDCDRR RXIF=1 RXBF=1
KEY: shaded data packets indicate a transmit by the MCU's DDC module
Figure 16-9. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor DDC12AB Interface
Data Sheet 249
DDC12AB Interface
Data Sheet 250 DDC12AB Interface
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 17. Sync Processor
17.1 Contents
17.2 17.3 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
17.5 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.5.1 Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.1 Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.2 Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.3 Composite Sync Polarity Detection . . . . . . . . . . . . . . . . 256 17.5.2 Sync Signal Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 17.5.3 Polarity Controlled HOUT and VOUT Outputs . . . . . . . . . . 257 17.5.4 Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17.5.5 Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . . 259 17.6 Sync Processor I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . 259 17.6.1 Sync Processor Control & Status Register (SPCSR). . . . . 259 17.6.2 Sync Processor Input/Output Control Register (SPIOCR) . 261 17.6.3 Vertical Frequency Registers (VFRs). . . . . . . . . . . . . . . . . 263 17.6.4 Hsync Frequency Registers (HFRs). . . . . . . . . . . . . . . . . . 265 17.6.5 Sync Processor Control Register 1 (SPCR1). . . . . . . . . . . 267 17.6.6 H & V Sync Output Control Register (HVOCR) . . . . . . . . . 268 17.7 System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 251
Sync Processor 17.2 Introduction
The Sync Processor is designed to detect and process sync signals inside a digital monitor system -- from separated Hsync and Vsync inputs. After detection and the necessary polarity correction and/or sync separation, the corrected sync signals are sent out. The MCU can also send commands to other monitor circuitry, such as for the geometry correction and OSD, using the DDC12AB and/or the IIC communication channels. The block diagram of the Sync Processor is shown in Figure 17-2.
NOTE:
All quoted timings in this section assume an internal bus frequency of 6MHz.
17.3 Features
Features of the Sync Processor include the following: * * * * * Polarity detector Horizontal frequency counter Vertical frequency counter Low vertical frequency indicator (40.7Hz) Polarity controlled HOUT and VOUT outputs: - From separate Hsync and Vsync - From composite sync on HSYNC input pin - From internal selectable free running Hsync and Vsync pulses * * * Free-running Hsync, Vsync, DE, and DCLK of 4 video modes CLAMP pulse output to the external pre-amp chip Internal schmitt trigger on HSYNC, and VSYNC input pins to improve noise immunity
Data Sheet 252 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor I/O Pins
17.4 I/O Pins
The Sync Processor uses seven I/O pins, with four pins shared with standard port I/O pins and one pin shared with timer channel 0. The full name of the Sync Processor I/O pins are listed in Table 17-1. The generic pin name appear in the text that follows. Table 17-1. Pin Name Conventions
Sync Processor Generic Pin Names: HSYNC VSYNC HOUT VOUT DE DCLK CLAMP Full MCU Pin Names: HSYNC VSYNC PTD3/HOUT PTD2/VOUT PTD1/DE PTD0/DCLK CLAMP/TCH0 Pin Selected for Sync Processor Function By: -- -- HOUTE bit in PDCR ($0069) VOUTE bit in PDCR ($0069) DEE bit in PDCR ($0069) DCLKE bit in PDCR ($0069) ELS0B and ELS0A bits in TSC0 ($0010)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 253
Sync Processor
Addr.
Register Name Read: Sync Processor Control and Status Register Write: (SPCSR) Reset: Read: Vertical Frequency High Register Write: (VFHR) Reset: Read: Vertical Frequency Low Register Write: (VFLR) Reset: Read: Hsync Frequency High Register Write: (HFHR) Reset:
Bit 7 VSIE 0 VOF
6 VEDGE
5 VSIF
4 COMP
3 VINVO 0 VF11
2 HINVO 0 VF10
1 VPOL
Bit 0 HPOL
$0040
0 0 0 CPW1 0 VF7 0 VF6 0 0 CPW0 0 VF5 0 VF4 0 VF3 0 VF2 0 VF1 0 VF0 0 VF12 0 VF9 0 VF8
$0041
$0042
0 HFH7
0 HFH6
0 HFH5
0 HFH4
0 HFH3
0 HFH2
0 HFH1
0 HFH0
$0043
0
0 0
0 0
0 HFL4
0 HFL3
0 HFL2
0 HFL1
0 HFL0
$0044
Read: HOVER Hsync Frequency Low Register Write: (HFLR) Reset: 0 Sync Processor I/O Control Write: Register (SPIOCR) Reset: Read: Sync Processor Control Register 1 Write: (SPCR1) Reset:
0
0 COINV
0 R
0 R
0 R
0 BPOR 0
0 SOUT 0 FSHF 0
Read: VSYNCS HSYNCS $0045
0 LVSIE
0 LVSIF
0 HPS1 HPS0 0 DCLKPH1 DCLKPH0 0 0 R = Reserved R R R
ATPOL 0
$0046
0 0 0 0
Read: H&V Sync Output Control $003F Register Write: (HVOCR) Reset: = Unimplemented
HVOCR1 HVOCR0 0 0
Figure 17-1. Sync Processor I/O Register Summary
Data Sheet 254 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Functional Blocks
17.5 Functional Blocks
EXTRACTED VSYNC VSYNC SVF A
1
A1 BS
VINVO
VOUT
BS
COMP
SOUT VSIF
POLARITY DETECT
VPOL VSIE EDGE DETECT
ONE SHOT VFLR INTERNAL BUS CLOCK 6MHz 125kHz VFHR
VEDGE VOF
/ 48
13-BIT COUNTER
OVERFLOW DETECT
$C00 DETECT LVSIF LVSIE TO INTERRUPT LOGIC
ONE SHOT CLK32/32.768 HSYNC HFLR HFHR HOVER
12-BIT COUNTER
OVERFLOW DETECT
POLARITY DETECT DE VPOL
B A1 S COMP
HPOL
EXTRACTED VSYNC DCLK SVF BPOR DCLK1 FROM CGM H/V SYNC, DE, DCLK PULSE GENERATOR SHF B A1 S SOUT HOUT COINV CLAMP PULSE GENERATOR CLAMP VSYNC EXTRACTOR
HVOCR[1:0]
DCLKPH[1:0]
HINVO
Figure 17-2. Sync Processor Block Diagram
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor Data Sheet 255
Sync Processor
17.5.1 Polarity Detection 17.5.1.1 Hsync Polarity Detection The Hsync polarity detection circuit measures the length of high and low period of the HSYNC input. If the length of high is longer than L and the length of low is shorter than S, the HPOL bit will be "0", indicating a negative polarity HSYNC input. If the length of low is longer than L and the length of high is shorter than S, the HPOL bit will be "1", indicating a positive polarity HSYNC input. The table below shows three possible cases for HSYNC polarity detection -- the conditions are selected by the HPS[1:0] bits in the Sync Processor Control Register 1 (SPCR1).
Polarity Detection Pulse Width Long is greater than (L) 7s 3.5s 14s Short is less than (S) 6s 3s 12s SPCR1 ($0046) HPS1 0 1 0 HPS0 0 X 1
17.5.1.2 Vsync Polarity Detection The Vsync polarity detection circuit performs a similar function as for Hsync. If the length of high is longer than 4ms and the length of low is shorter than 2ms, the VPOL bit will be "0", indicating a negative polarity VSYNC input. If the length of low is longer than 4ms and the length of high is shorter than 2ms, the VPOL bit will be "1", indicating a positive polarity VSYNC input. 17.5.1.3 Composite Sync Polarity Detection When a composite sync signal is the input (COMP = 1 for composite sync processing), the HPOL bit = VPOL bit, and the polarity is detected using the VSYNC polarity detection criteria described in section 17.5.1.2 .
Data Sheet 256 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Functional Blocks
17.5.2 Sync Signal Counters There are two counters: a 13-bit horizontal frequency counter to count the number of horizontal sync pulses within a 32ms or 8ms period; and a 13-bit vertical frequency counter to count the number of system clock cycles between two vertical sync pulses. These two data can be read by the CPU to check the signal frequencies and to determine the video mode. The 13-bit vertical frequency register encompasses vertical frequency range from approximately 15Hz to 128kHz. Due to the asynchronous timing between the incoming VSYNC signal and internal system clock, there will be 1 count error on reading the Vertical Frequency Registers (VFRs) for the same vertical frequency. The horizontal counter counts the pulses on HSYNC pin input, and is uploaded to the Hsync Frequency Registers (HFRs) every 32.768ms or 8.192ms.
17.5.3 Polarity Controlled HOUT and VOUT Outputs The processed sync signals are output on HOUT and VOUT when the corresponding bits in Configuration Register 0 ($0069) are set. The signal to these output pins depend on SOUT and COMP bits (see Table 17-2), with polarity controlled by ATPOL, HINVO, and VINVO bits as shown in Table 17-3. Table 17-2. Sync Output Control
SOUT 1 0 COMP X 0 Sync Outputs: VOUT and HOUT Free-running video mode output Sync outputs follow sync inputs VSYNC and HSYNC respectively, with polarity correction shown in Table 17-3. HOUT follows the composite sync input and VOUT is the extracted Vsync (3 to 14s delay to composite input), with polarity correction shown in Table 17-3.
0
1
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 257
Sync Processor
Table 17-3. Sync Output Polarity
ATPOL X 0 0 1 1 SOUT 1 0 0 0 0 VINVO or HINVO X 0 1 0 1 Sync Outputs: VOUT/HOUT Free-running video mode output Same polarity as sync input Inverted polarity of sync input Negative polarity sync output Positive polarity sync output
When the SOUT bit is set, the HOUT output is a free-running pulse. Both HOUT and VOUT outputs are negative polarity, with frequencies selected by the H & V Sync Output Control Register (HVOCR). 17.5.4 Clamp Pulse Output When the ELS0B and ELS0A bits in the TSC0 register are logic 0 (see Table 11-3), a clamp signal is output on the CLAMP pin. This clamp pulse is triggered either on the leading edge or the trailing edge of HSYNC, controlled by BPOR bit, with the polarity controlled by the COINV bit. See Figure 17-3 . Clamp Pulse Output Timing.
HSYNC (HPOL = 1) CLAMP (BPOR = 0)
Pulse width = 0.33~2.1s
CLAMP (BPOR = 1) HSYNC (HPOL = 0) CLAMP (BPOR = 0)
Pulse width = 0.33~2.1s
Pulse width = 0.33~2.1s
CLAMP (BPOR = 1)
Pulse width = 0.33~2.1s
Figure 17-3. Clamp Pulse Output Timing
Data Sheet 258 Sync Processor MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Sync Processor I/O Registers
17.5.5 Low Vertical Frequency Detect Logic monitors the value of the Vsync Frequency Register (VFR), and sets the low vertical frequency flag (LVSIF) when the value of VFR is higher than $C00 (frequency below 40.7Hz). LVSIF bit can generate an interrupt request to the CPU when the LVSIE bit is set and I-bit in the Condition Code Register is "0". The LVSIF bit can help the system to detect video off mode fast.
17.6 Sync Processor I/O Registers
Eight registers are associated with the Sync Processor, they outlined in the following sections.
17.6.1 Sync Processor Control & Status Register (SPCSR)
Address: $0040 Bit 7 Read: VSIE Write: Reset: 0 0 VEDGE 0 0 0 0 0 0 0 6 5 VSIF COMP VINVO HINVO 4 3 2 1 VPOL Bit 0 HPOL
= Unimplemented
Figure 17-4. Sync Processor Control & Status Register (SPCSR) VSIE -- VSync Interrupt Enable When this bit is set, the VSIF flag is enabled to generate an interrupt request to the CPU. When VSIE is cleared, the VSIF flag is prevented from generating an interrupt request to the CPU. Reset clears this bit. 1 = VSIF bit set will generate interrupt request to CPU 0 = VSIF bit set does not generate interrupt request to CPU
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 259
Sync Processor
VEDGE -- VSync Interrupt Edge Select This bit specifies the triggering edge of Vsync interrupt. When it is "0", the rising edge of internal Vsync signal which is either from the VSYNC pin or extracted from the composite input signal will set VSIF flag. When it is "1", the falling edge of internal Vsync signal will set VSIF flag. Reset clears this bit. 1 = VSIF bit will be set by falling edge of Vsync 0 = VSIF bit will be set by rising edge of Vsync VSIF -- VSync Interrupt Flag This flag is only set by the specified edge of the internal Vsync signal, which is either from the VSYNC input pin or extracted from the composite sync input signal. The triggering edge is specified by the VEDGE bit. VSIF generates an interrupt request to the CPU if the VSIE bit is also set. This bit is cleared by writing a "0" to it or by a reset. 1 = A valid edge is detected on the Vsync 0 = No valid Vsync is detected COMP -- Composite Sync Input Enable This bit is set to enable the separator circuit which extracts the Vsync pulse from the composite sync input on HSYNC. The extracted Vsync signal is used as it were from the VSYNC input. Reset clears this bit. 1 = Composite sync input enabled 0 = Composite sync input disabled VINVO -- VOUT Signal Polarity This bit, together with the ATPOL bit in SPCR1 controls the output polarity of the VOUT signal (see Table 17-4). HINVO -- HOUT Signal Polarity This bit, together with the ATPOL bit in SPCR1 controls the output polarity of the HOUT signal (see Table 17-4).
Data Sheet 260 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Sync Processor I/O Registers
Table 17-4. ATPOL, VINVO, and HINVO setting
ATPOL 0 0 1 1 VINVO / HINVO 0 1 0 1 Sync Outputs: VOUT/HOUT Same polarity as sync input Inverted polarity of sync input Negative polarity sync output Positive polarity sync output
VPOL -- Vsync Input Polarity This bit indicates the polarity of the VSYNC input, or the extracted Vsync from a composite sync input (COMP=1). Reset clears this bit. 1 = Vsync is positive polarity 0 = Vsync is negative polarity HPOL -- Hsync Input Polarity This bit indicates the polarity of the HSYNC input. This bit equals the VPOL bit when the COMP bit is set. Reset clears this bit. 1 = Hsync is positive polarity 0 = Hsync is negative polarity
17.6.2 Sync Processor Input/Output Control Register (SPIOCR)
Address: $0045 Bit 7 6 5 COINV Write: Reset: 0 0 0 R = Reserved 0 0 4 R 3 R 2 R 1 BPOR Bit 0 SOUT
Read: VSYNCS HSYNCS
= Unimplemented
Figure 17-5. Sync Processor Input/Output Control Register (SPIOCR) VSYNCS -- VSYNC Input State This read-only bit reflects the logical state of the VSYNC input. HSYNCS -- HSYNC Input State This read-only bit reflects the logical state of the HSYNC input.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor Data Sheet 261
Sync Processor
COINV -- Clamp Output Invert This bit is set to invert the clamp pulse output to negative. Reset clears this bit. 1 = Clamp output is set for negative pulses 0 = Clamp output is set for positive pulses BPOR -- Back Porch This bit defines the triggering edge of the clamp pulse output relative to the HSYNC input. Reset clears this bit. 1 = Clamp pulse is generated on the trailing edge of HSYNC 0 = Clamp pulse is generated on the leading edge of HSYNC SOUT -- Sync Output Enable This bit will select the output signals for the VOUT and HOUT pins and generate the DE and DCLK signals to the pins. Reset clears this bit. 1 = VOUT, HOUT, DE, and DCLK outputs are internally generated free-running timing pulses with frequencies determined by HVCOR[1:0] bits in HVCOR and CGM values. 0 = VOUT and HOUT outputs are processed VSYNC and HSYNC inputs respectively and DE and DCLK are hold as logic low.
Data Sheet 262 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Sync Processor I/O Registers
17.6.3 Vertical Frequency Registers (VFRs) This register pair contains the 13-bit vertical frequency count value, an overflow bit, and the clamp pulse width selection bits.
Address: $0041 Bit 7 Read: Write: Reset: 0 VOF 6 0 CPW1 0 5 0 CPW0 0 0 0 0 0 0 4 VF12 3 VF11 2 VF10 1 VF9 Bit 0 VF8
Figure 17-6. Vertical Frequency High Register
Address: $0042 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 VF7 6 VF6 5 VF5 4 VF4 3 VF3 2 VF2 1 VF1 Bit 0 VF0
= Unimplemented
Figure 17-7. Vertical Frequency Low Register VF[12:0] -- Vertical Frame Frequency This read-only 13-bit contains information of the vertical frame frequency. An internal 13-bit counter counts the number of 8s periods between two Vsync pulses. The most significant 5 bits of the counted value is transferred to the high byte register, and the least significant 8 bits is transferred to an intermediate buffer. When the high byte register is read, the 8-bit counted value stored in the intermediate buffer will be uploaded to the low byte register. Therefore, user program must read the high byte register first, then low byte register in order to get the complete counted value of one vertical frame. If the counter overflows, the overflow flag, VOF, will be set, indicating the counter value stored in the VFRs is meaningless. The data corresponds to the period of one vertical frame. This register can be read to determine if the frame frequency is valid, and to determine the video mode.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 263
Sync Processor
The frame frequency is calculated by: 1 Vertical Frame Frequency = -------------------------------------------------VFR 1 x 48 x t CYC 1 = ------------------------------------VFR 1 x 8 s
for internal bus clock of 6MHz
Table 17-5 shows examples for the Vertical Frequency Register, all VFR numbers are in hexadecimal.
Table 17-5. Sample Vertical Frame Frequencies
VFR $02A0 $03C0 $03C1 $03C2 $04E2 $04E3 $04E4 $06F9 $06FA $06FB Max Freq. 186.20 Hz 130.34 Hz 130.21 Hz 130.07 Hz 100.08 Hz 100.00 Hz 99.92 Hz 70.07 Hz 70.03 Hz 69.99 Hz Min Freq. 185.70 Hz 130.07 Hz 129.94 Hz 129.80 Hz 99.92 Hz 99.84 Hz 99.76 Hz 69.99 Hz 69.95 Hz 69.91 Hz VFR $0780 $0823 $0824 $0825 $09C4 $09C5 $09C6 $1FFD $1FFE $1FFF Max Freq. 65.10 Hz 60.04 Hz 60.01 Hz 59.98 Hz 50.02 Hz 50.00 Hz 49.98 Hz 15.266 Hz 15.264 Hz 15.262 Hz Min Freq. 65.00 Hz 59.98 Hz 59.95 Hz 59.92 Hz 49.98 Hz 49.96 Hz 49.94 Hz 15.262 Hz 15.260 Hz 15.258 Hz
VOF -- Vertical Frequency Counter Overflow This read-only bit is set when an overflow has occurred on the 13-bit vertical frequency counter. Reset clears this bit, and will be updated every vertical frame. An overflow occurs when the period of Vsync frame exceeds 64.768ms (a vertical frame frequency lower than 15.258Hz). 1 = A vertical frequency counter overflow has occurred 0 = No vertical frequency counter overflow has occurred
Data Sheet 264 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Sync Processor I/O Registers
CPW[1:0] -- Clamp Pulse Width The CPW1 and CPW0 bits are used to select the output clamp pulse width. Reset clears these bits, selecting a default clamp pulse width between 0.33s and 0.375s. These bits always read as Zeros. Table 17-6. Clamp Pulse Width
CPW1 0 0 1 1 CPW0 0 1 0 1 Clamp Pulse Width 0.33s to 0.375s 0.5s to 0.542s 0.75s to 0.792s 2s to 2.042s
17.6.4 Hsync Frequency Registers (HFRs) This register pair contains the 13-bit Hsync frequency count value and an overflow bit.
Address: $0043 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 HFH7 6 HFH6 5 HFH5 4 HFH4 3 HFH3 2 HFH2 1 HFH1 Bit 0 HFH0
Figure 17-8. Hsync Frequency High Register
Address: $0044 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 HOVER 6 0 5 0 4 HFL4 3 HFL3 2 HFL2 1 HFL1 Bit 0 HFL0
= Unimplemented
Figure 17-9. Hsync Frequency Low Register
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 265
Sync Processor
HFH[7:0], HFL[4:0] -- Horizontal Line Frequency This read-only 13-bit contains the number of horizontal lines in a 32ms window. An internal 13-bit counter counts the Hsync pulses within a 32ms window in every 32.768ms period. If the FSHF bit in SPCR1 is set, only the most 11-bits (HFH[7:0] & HFL[4:2]) will be updated by the counter. Thus, providing a Hsync pulse count in a 8ms window in every 8.192ms. The most significant 8 bits of counted value is transferred to the high byte register, and the least significant 5 bits is transferred to an intermediate buffer. When the high byte register is read, the 5-bit counted value stored in the intermediate buffer will be uploaded to the low byte register. Therefore, user the program must read the high byte register first then low byte register in order to get the complete counted value of Hsync pulses. If the counter overflows, the overflow flag, HOVER, will be set, indicating the number of Hsync pulses in 32ms are more than 8191 (213 -1), i.e. a Hsync frequency greater than 256kHz. For the 32ms window, the HFHR and HFLR are such that the frequency step unit in the 5-bit of HFLR is 0.03125kHz, and the step unit in the 8-bit HFHR is 1kHz. Therefore, the Hsync frequency can be easily calculated by: Hsync Frequency = [HFH + (HFL x 0.03125)] kHz
where: HFH is the value of HFH[7:0] HFL is the value of HFL[4:0]
HOVER -- Hsync Frequency Counter Overflow This read-only bit is set when an overflow has occurred on the 13-bit Hsync frequency counter. Reset clears this bit, and will be updated every count period. An overflow occurs when the number Hsync pulses exceed 8191, a Hsync frequency greater than 256kHz. 1 = A Hsync frequency counter overflow has occurred 0 = No Hsync frequency counter overflow has occurred
Data Sheet 266 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor Sync Processor I/O Registers
17.6.5 Sync Processor Control Register 1 (SPCR1)
Address: $0046 Bit 7 Read: LVSIE Write: Reset: 0 0 0 0 0 R = Reserved 0 0 6 LVSIF HPS1 HPS0 R R ATPOL FSHF 5 4 3 2 1 Bit 0
= Unimplemented
Figure 17-10. Sync Processor Control Register 1 (SPCR1) LVSIE -- Low VSync Interrupt Enable When this bit is set, the LVSIF flag is enabled to generate an interrupt request to the CPU. When LVSIE is cleared, the LVSIF flag is prevented from generating an interrupt request to the CPU. Reset clears this bit. 1 = Low Vsync interrupt enabled 0 = Low Vsync interrupt disabled LVSIF -- Low VSync Interrupt Flag This read-only bit is set when the value of VFR is higher than $C00 (vertical frame frequency below 40.7Hz). LVSIF generates an interrupt request to the CPU if the LVSIE is also set. This bit is cleared by writing a "0" to it or reset. 1 = Vertical frequency is below 40.7Hz 0 = Vertical frequency is higher than 40.7Hz HPS[1:0] -- HSYNC input Detection Pulse Width These two bits control the detection pulse width of HSYNC input. Reset clears these two bits, setting a default middle frequency of HSYNC input. Table 17-7. HSYNC Polarity Detection Pulse Width
HPS1 0 1 0 HPS0 0 X 1 Polarity Detection Pulse Width Long > 7s and Short < 6s Long > 3.5s and Short < 3s Long > 14s and Short < 12s
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor
Data Sheet 267
Sync Processor
ATPOL -- Auto Polarity This bit, together with the VINVO or HINVO bits in SPCSR controls the output polarity of the VOUT or HOUT signals respectively. Reset clears this bit (see Table 17-8). Table 17-8. ATPOL, VINVO, and HINVO setting
ATPOL 0 0 1 1 VINVO / HINVO 0 1 0 1 Sync Outputs: VOUT/HOUT Same polarity as sync input Inverted polarity of sync input Negative polarity sync output Positive polarity sync output
FSHF -- Fast Horizontal Frequency Count This bit is set to shorten the measurement cycle of the horizontal frequency. If it is set, only HFH[7:0] and HFL[4:2] will be updated by the Hsync counter, providing a count in a 8ms window in every 8.192ms, with HFL[1:0] reading as zeros. Therefore, user can determine the horizontal frequency change within 8.192ms to protect critical circuitry. Reset clears this bit. 1 = Number of Hsync pulses is counted in an 8ms window 0 = Number of Hsync pulses is counted in a 32ms window
17.6.6 H & V Sync Output Control Register (HVOCR)
Address: $003F Bit 7 Read: DCLKPH1 DCLKPH0 Write: Reset: = Unimplemented 0 0 R = Reserved 0 0 R HVOCR1 HVOCR0 6 5 4 3 2 1 Bit 0
Figure 17-11. H&V Sync Output Control Register (HVOCR)
Data Sheet 268 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Sync Processor System Operation
DCLKPH[1:0] -- DCLK Output Phase Adjustment These two bits are programmed to adjust the DCLK output phase. Each increment adds approximately 2 to 3ns delay to the DCLK output. HVOCR[1:0] -- Free Running Video Mode Select Bits These two bits together with MUL[7:4] and VRS[7:4] in CGM's PLL programming register determine the frequencies of the internal generated free-running signals for output to HOUT, VOUT, DE, and DCLK pins, when the SOUT bit is set in the sync processor I/O control register. These two bits determine the prescaler of PLL reference clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2; for other values, the prescaler is 3. Reset clears these bits, setting a default horizontal frequency of 31.25kHz and a vertical frequency of 60Hz, a video mode of 640x480. (See Section 8. Clock Generator Module (CGM).) Table 17-9. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
HVOCR[1:0] 00 01 10 11 MUL[7:4] 3 5 8 9 VRS[7:4] 3 3 6 9 HOUT Frequency 31.45kHz 37.87kHz 48.37kHz 64.32kHz VOUT Frequency 59.91Hz 60.31Hz 60.31Hz 60.00Hz DCLK Frequency 24MHz 40MHz 64MHz 108MHz DE Video Mode VGA 640 x 480 SVGA 800 x 600 XGA 1024 x 768 SXGA 1280 x 1024
17.7 System Operation
This Sync Processor is designed to assist in determining the video mode of incoming HSYNC and VSYNC of various frequencies and polarities, and DPMS modes. In the DPMS standard, a no sync pulses definition can be detected when the value of the Hsync Frequency Register (the number of Hsync pulses) is less than one or when the VOF bit is set. Since the Hsync Frequency Register is updated repeatedly in every 32.768ms, and a valid Vsync must have a frequency greater than 40.7Hz, a valid Vsync pulse will arrive within the 32.768ms window. Therefore, the user should read the Hsync Frequency Register every 32.768ms to determine the presence of Hsync and/or Vsync pulses.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Sync Processor Data Sheet 269
Sync Processor
Data Sheet 270 Sync Processor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 18. On-Screen Display (OSD)
18.1 Contents
18.2 18.3 18.4 18.5 18.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 OSD FLASH Font Memory Map . . . . . . . . . . . . . . . . . . . . . . . 275 OSD Screen Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
18.7 OSD Module I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .277 18.7.1 OSD Control Register (OSDCR) . . . . . . . . . . . . . . . . . . . . 277 18.7.2 OSD Status Register (OSDSR) . . . . . . . . . . . . . . . . . . . . . 278 18.7.3 OSD Data Registers (OSDDRH:OSDDRL) . . . . . . . . . . . . 279 18.7.4 OSD Row Address Register (OSDRAR) . . . . . . . . . . . . . . 280 18.7.5 OSD Column Address Register (OSDCAR). . . . . . . . . . . . 280 18.7.6 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) . 281 18.8 OSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.8.1 OSD Display Registers (Attribute and Code Registers) . . . 282 18.8.2 Row Attribute Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.8.3 Control, Window, and Pattern Registers . . . . . . . . . . . . . . 283 18.8.3.1 Window Registers 1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . 284 18.8.3.2 Vertical Delay Control Register . . . . . . . . . . . . . . . . . . . 285 18.8.3.3 Horizontal Delay Control Register . . . . . . . . . . . . . . . . . 286 18.8.3.4 Character Height Control Register . . . . . . . . . . . . . . . . . 286 18.8.3.5 Frame Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 288
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
Data Sheet 271
On-Screen Display (OSD) 18.2 Introduction
This section describes the on-screen display (OSD) module. This module includes a 15 row x 30 column display window and video pattern generator.
18.3 Features
Features of the on-screen display module include: * * * * * * * * * * * Up to 384 fonts: 12 x 16 or 16 x 16 Resolution: up to 2048 dots/line Scan lines per frame: up to 2048 lines Fully programmable display character array of 15 rows by 30 columns Eight selections of color for menu windows and fonts Row to row spacing control Four programmable background windows Window shadowing with programmable width, height, and color Programmable vertical and horizontal positioning for display center Full screen pattern output of free-running VGA, SVGA, XGA, SXGA timing from Sync Processor module Double character height and double character width
Data Sheet 272 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) System Overview
Addr.
Register Name
Bit 7
6 R
5 OSDRST 0
4 CLKINV 0
3 CLKPH1 0
2
1
Bit 0
$0060
Read: OSDMEN OSD Control Register Write: (OSDCR) Reset: 0 Read: OSD Status Register Write: (OSDSR) Reset: WRDY
CLKPH0 HALFCLK OSDIEN 0 0 0 DENDIF 0
$0061
1 OSDD6 OSDD5 OSDD4 OSDD3 OSDD2 OSDD1
0 OSDD0
$0062
Read: OSDD7 OSD Data Register Low Write: (OSDDRL) Reset: Read: OSDD15 OSD Data Register High Write: (OSDDRH) Reset: Read: OSD Row Address Register Write: (OSDRAR) Reset: Read: OSD Column Address Register Write: (OSDCAR) Reset: Read: OSD FLASH Even DOT15 High Byte Write Buffer Write: (OSDEHBUF) Reset:
Unaffected by reset OSDD14 OSDD13 OSDD12 OSDD11 OSDD10 OSDD9 OSDD8
$0063
Unaffected by reset ROWA3 0 COLA4 0 DOT14 DOT13 DOT12 COLA3 0 DOT11 ROWA2 0 COLA2 0 DOT10 ROWA1 0 COLA1 0 DOT9 ROWA0 0 COLA0 0 DOT8
$0064
$0065
$0066
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 18-1. On-Screen Display I/O Register Summary
18.4 System Overview
The OSD module has a full screen memory architecture. Refresh is done by the built-in synchronous circuitry. The full screen display data can be updated through writing row, column, and data buffers. Thus, the display data can be updated randomly afterward. Figure 18-2 shows the block diagram of the OSD module.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
Data Sheet 273
On-Screen Display (OSD)
INTERNAL BUS
$0060 Bit7
OSDMEN
$0062 $0063 $0064 $0065
ROW AND COLUMN ADDRESS AND DATA BUFFERS CONTROL LOGIC
PHSYNC
PVSYNC
SHIFT REGISTER
Row and Column ROW AND COLUMN Address 16 ROW x 32 COLUMN Code 16 x 16 ADDRESS ATTRIBUTE AND CODE 384 FONTS GENERATOR DISPLAY RAM FLASH MEMORY
PCLK
CLOCK GENERATOR
ROW ATTRIBUTE LATCHES OUTPUT LOGIC FRAME ATTRIBUTE PATTERN GENERATOR CONTROL
OSDR
OSDG
OSDB
FBKG
Figure 18-2. OSD Block Diagram User program must write the row and column addresses to the row and column address registers, then write the code and attributes to the 16-bit OSD data register to complete one display character or symbol update. The WRDY bit will then be set to acknowledge that the data has been updated to the addressed display RAM. This process is repeated for other updates.
Data Sheet 274 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD FLASH Font Memory Map
18.5 OSD FLASH Font Memory Map
The 12K-byte FLASH memory from $1000 to $3FFF is for OSD font storage. This OSD font memory stores up to 384 fonts, with each font made up of 16 lines by 16 bits, i.e. 32 memory locations. The OSD fonts memory can be accessed by CPU when the OSDMEN bit in the OSD control register is clear. See 18.7.6 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) for how to program the OSD font memory.
Character Code $0000 Font Memory Address $1000 - $1001 $1002 - $1003 $1004 - $1005 $1006 - $1007 $1008 - $1009 $100A - $100B $100C - $100D $100E - $100F $1010 - $1011 $1012 - $1013 $1014 - $1015 $1016 - $1017 $1018 - $1019 $101A - $101B $101C - $101D $101E - $101F $1020 - $1021 $1022 - $1023 $1024 - $1025 $1026 - $1027 $1028 - $1029 $102A - $102B $102C - $102D $102E - $102F $1030 - $1031 $1032 - $1033 $1034 - $1035 $1036 - $1037 $1038 - $1039 $103A - $103B $103C - $103D $103E - $103F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Even Byte Odd Byte Dot
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
$0001
$0002
$017F
$3FE0 - $3FE1 $3FE2 - $3FE3 $3FE4 - $3FE5 $3FE6 - $3FE7 $3FE8 - $3FE9 $3FEA - $3FEB $3FEC - $3FED $3FEE - $3FEF $3FF0 - $3FF1 $3FF2 - $3FF3 $3FF4 - $3FF5 $3FF6 - $3FF7 $3FF8 - $3FF9 $3FFA - $3FFB $3FFC - $3FFD $3FFE - $3FFF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 18-3. Memory Map of OSD FLASH Fonts
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD) Data Sheet 275
16 lines
16 lines
On-Screen Display (OSD) 18.6 OSD Screen Memory Map
The OSD operating screen is mapped to a 1K-byte RAM array from $0800 to $0BFF. The array is organized as 16 rows by 32 columns, with two bytes (16-bit) for each row-column location. Figure 18-4 shows the OSD screen memory map.
COLUMN $800 DISPLAY RAM ADDRESS $840 - $87F $880 - $8BF $8C0 - $8FF $900 - $93F $940 - $97F $980 - $9BF $9C0 - $9FF $A00 - $A3F $A40 - $A7F $A80 - $ABF $AC0 - $AFF $B00 - $B3F $B40 - $B7F $B80 - $BBF NOT MAPPED ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 $801 $802 1 $803 $804 2 $805 $806 3 $807 28 $838 $839 29 $83C $83A $83B 30 $83D $83E 31 $83F
A A A A A A A A A A A A A A A
C C C C C C C C C C C C C C C
ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC ACACAC ACAC CONTROL, WINDOW, AND PATTERN REGISTERS
DISPLAY
REGISTERS
A = Character ATTRIBUTE
C = Character CODE
Figure 18-4. Memory Map of OSD Registers The area covering row0-column0 and row14-column29 are called the active display registers. Each 16-bit display register defines the character to be displayed, with an character code (character from font memory) and an attribute code for that character. Column30 of each row is the attribute register for the entire row. Row15 registers (not memory mapped) are used for control, window, and pattern for the entire OSD screen. See 18.8 OSD Registers for register definitions. The CPU have direct access to the all screen memory registers ($0800 to $0BFF) when the OSDMEN bit in the OSD control register is clear. When the OSD circuitry is displaying the characters (OSDMEN=1), updates to display is by indirectly writing to these registers. The OSD data registers, row register, column register are used for this purpose. See 18.7.3 OSD Data Registers (OSDDRH:OSDDRL), 18.7.4 OSD Row Address Register (OSDRAR), and 18.7.5 OSD Column Address Register (OSDCAR).
Data Sheet 276 On-Screen Display (OSD) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
ROW ATTRIBUTE REGISTERS
On-Screen Display (OSD) OSD Module I/O Registers
18.7 OSD Module I/O Registers
Seven registers are associated with the OSD module, they outlined in the following sections.
18.7.1 OSD Control Register (OSDCR)
Address: $0060 Bit 7 Read: OSDMEN Write: Reset: 0 0 0 0 0 0 0 R OSDRST CLKINV CLKPH1 CLKPH0 HALFCLK OSDIEN 6 5 4 3 2 1 0
Figure 18-5. OSD Control Register (OSDCR) OSDMEN -- OSD Memory Enable When this bit is clear, the OSD RAM and font FLASH memory is directly under CPU access. When OSDMEN is set, OSD circuitry has read control over the OSD RAM and font FLASH memory for displaying the contents; CPU access is indirect, by writing to address and data buffers. The OSDMEN bit should be cleared while no OSD are displaying. Reset clear this bit. 1 = OSD RAM and font FLASH is under OSD circuitry access 0 = OSD RAM and font FLASH is directly under CPU access OSDRST -- OSD Module Reset Setting this bit resets the entire OSD logic and row15 registers (row1 to row14 registers are unaffected), and holds the OSD in the reset state. The input PCLK clock is prevented from entering the OSD module to reduce power consumption. Reset clear this bit. 1 = Reset OSD logic and row15 registers 0 = No effect CLKINV -- Pixel Clock Inversion This bit is set to invert the PCLK input of OSD. Reset clears this bit. 1 = PCLK input inverted 0 = PCLK input not inverted
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD) Data Sheet 277
On-Screen Display (OSD)
CLKPH[1:0] -- Pixel Clock Phase Adjustment These two bits adjust the pixel clock phase to the OSD module. Thus the OSDR, OSDG, and OSDB outputs can be in phase with video signals. Reset clears all these bits. HALFCLK -- Half Frequency of Pixel Clock This bit is set to divide the incoming pixel clock by two as the OSD display clock. Reset clears this bit. 1 = OSD module display clock is PCLK divided-by-2 0 = OSD module display clock is PCLK divided-by-1 OSDIEN -- OSD Interrupt Enable This bit enable OSD interrupt when DENDIF in the OSD status register is set. Reset clear this bit. 1 = DENDIF bit set will generate interrupt request to CPU 0 = DENDIF bit set will not generate interrupt request to CPU
18.7.2 OSD Status Register (OSDSR)
Address: $0061 Bit 7 Read: Write: Reset: 1 = Unimplemented WRDY 6 5 4 3 2 1 0 DENDIF 0 0
Figure 18-6. OSD Status Register (OSDSR) WRDY -- OSD Buffer Write Ready This bit is set when the OSD data registers, $0062 and $0063, are ready to be loaded with new data. The WRDY is cleared after the CPU writes to the low byte register, $0062. It becomes set again when the OSD circuitry has transferred the content of data registers to the display RAM. Reset sets this bit. 1 = OSD data buffers ready for new data 0 = OSD data buffers busy
Data Sheet 278 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Module I/O Registers
DENDIF -- OSD Display End Interrupt Flag This bit is set when the OSD has finished the row15 display; it is cleared by writing a logic 0 to it. The DENDIF bit is designed for user program to update the OSD RAM while not displaying OSD. Reset clears this bit. 1 = OSD has finished the row15 display 0 = No effect
18.7.3 OSD Data Registers (OSDDRH:OSDDRL)
Address: $0063 Bit 7 Read: OSDD15 Write: Reset: Unaffected by reset OSDD14 OSDD13 OSDD12 OSDD11 OSDD10 OSDD9 OSDD8 6 5 4 3 2 1 0
Figure 18-7. OSD Data Register High (OSDDRH)
Address: $0062 Bit 7 Read: OSDD7 Write: Reset: Unaffected by reset OSDD6 OSDD5 OSDD4 OSDD3 OSDD2 OSDD1 OSDD0 6 5 4 3 2 1 0
Figure 18-8. OSD Data Register Low (OSDDRL) OSDD[15:0] -- OSD RAM 16-Bit Data Buffer While OSD circuitry is displaying data from the display RAM, update the display RAM (location specified by the row and column address registers, OSDRAR and OSDCAR) by writing data to the high byte register (OSDDRH) followed by the low byte register (OSDDRL). After writing to the OSDDRL, the OSD buffer write ready bit (WRDY) will be cleared. WRDY becomes set again when the OSD circuitry has transferred the content of the OSD data registers to the display RAM. Reset has no effect on these bits. (See 18.6 OSD Screen Memory Map.)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
Data Sheet 279
On-Screen Display (OSD)
18.7.4 OSD Row Address Register (OSDRAR)
Address: $0064 Bit 7 Read: ROWA3 Write: Reset: 0 0 0 0 ROWA2 ROWA1 ROWA0 6 5 4 3 2 1 0
Figure 18-9. OSD Row Address Register (OSDRAR) ROWA[3:0] -- OSD RAM Row Address These bits define the row address of the OSD RAM. Together with the column address, the row-column address defines the location in the OSD screen memory where data is to be transferred from the data buffers (OSD data registers). Data is transferred when the high byte data register is written ($0063). Reset clears these bits to zero. (See 18.6 OSD Screen Memory Map.)
18.7.5 OSD Column Address Register (OSDCAR)
Address: $0065 Bit 7 Read: COLA4 Write: Reset: 0 0 0 0 0 COLA3 COLA2 COLA1 COLA0 6 5 4 3 2 1 0
Figure 18-10. OSD Column Address Register (OSDCAR) COLA[4:0] -- OSD RAM Column Address These bits define the column address of the OSD RAM. Together with the row address, the row-column address defines the location in the OSD screen memory where data is to be transferred from the data buffers (OSD data registers). Data is transferred when the high byte data register is written ($0063). Reset clears these bits to zero. (See 18.6 OSD Screen Memory Map.)
Data Sheet 280 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Module I/O Registers
18.7.6 OSD FLASH Even High Byte Write Buffer (OSDEHBUF)
Address: $0066 Bit 7 Read: DOT15 Write: Reset: Unaffected by reset DOT14 DOT13 DOT12 DOT11 DOT10 DOT9 DOT8 6 5 4 3 2 1 0
Figure 18-11. OSD FLASH Even High Byte Write Buffer (OSDEHBUF) DOT[15:8] -- OSD FLASH Even High Byte Buffer These bits define the even byte for a single line of OSD font, to be programmed to the OSD FLASH memory. Reset has no effect on these bits. Figure 18-12 shows an example of an OSD font.
OSDEHBUF DOT15 DOT14 DOT13 DOT12 DOT11 DOT10 DOT9 DOT8
Font Memory Address $1000 - $1001 $1002 - $1003 $1004 - $1005 $1006 - $1007 $1008 - $1009 $100A - $100B $100C - $100D $100E - $100F $1010 - $1011 $1012 - $1013 $1014 - $1015 $1016 - $1017 $1018 - $1019 $101A - $101B $101C - $101D $101E - $101F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Even Byte
Odd Byte Dot
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 18-12. OSD Font Even Byte Buffer The OSDEHBUF register is a buffer for temporarily storing the even byte (or high byte) of an OSD font line to be programmed to the OSD FLASH memory. A 16-bit OSD font line is programmed by writing the even byte to OSDEHBUF, followed by a FLASH programming routine to the odd byte in the font memory. Programming the odd byte will automatic program the even byte. See 18.5 OSD FLASH Font Memory Map for OSD font memory map and Section 4. FLASH Memory on FLASH programming.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
16 lines
Data Sheet 281
On-Screen Display (OSD) 18.8 OSD Registers
The following sections define the OSD registers for display control as illustrated in Figure 18-4 . Memory Map of OSD Registers. 18.8.1 OSD Display Registers (Attribute and Code Registers) The OSD active display registers consist of 450 attribute and code registers in a 15 row by 30 column matrix. These registers are memory mapped to RAM locations as illustrated in Figure 18-4. When OSDMEN=0 (not displaying), CPU has direct access to these registers by reading/writing the RAM locations. When OSDMEN=1 (displaying), CPU access these registers indirectly by writing to the OSD data registers, row register and column register. Each attribute and code register affects one display character. Row 0-14, Column 0-29:
15 14 13 12 FSS 11 R 10 G 9 B 8 7 6 5 4 CRADDR CHARACTER CODE 3 2 1 0
BGR BGG BGB
CHARACTER ATTRIBUTE
CRADDR -- Character Address These bits form an address to select one of the 384 characters/symbols available from the FLASH font memory. BGR, BGG, BGB -- Character Background Color These bits define the color of the background of the associated character/symbol. When all three bits are clear, no background will be shown. Therefore, seven background colors can be selected. FSS -- Font Size This bit will determine the font size of the associated character/symbol. Reset clears this bit. 1 = The font size is 12 x 16 (DOT13 to DOT2) 0 = The font size is 16 x 16 R, G, B -- Character Color These bits define the color of the associated character/symbol.
Data Sheet 282 On-Screen Display (OSD) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Registers
18.8.2 Row Attribute Registers The 15 row attribute registers are at column 30 of the display rows. These registers are memory mapped to RAM locations as illustrated in Figure 18-4. When OSDMEN=0 (not displaying), CPU has direct access to these registers by reading/writing the RAM locations. When OSDMEN=1 (displaying), CPU access these registers indirectly by writing to the OSD data registers, row register and column register. Each row attribute register affects characters of a display row. Row 0-14, Column 30:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN CHS CWS
REN -- Row Enable Set this bit to enable OSD circuitry to display the current row of characters. This bit should be cleared when display RAM is accessed directly by the CPU and when the row points to a font that is to be updated in the FLASH font memory. 1 = Enable display for this row 0 = Disable display for this row CHS -- Character Height Set this bit to display double height characters for this row. 1 = Display characters as double height for this row 0 = Display characters as normal height for this row CWS -- Character Width Set this bit to display double width characters for this row. 1 = Display characters as double width for this row 0 = Display characters as normal width for this row 18.8.3 Control, Window, and Pattern Registers Row-15 registers are for window, pattern, and miscellaneous control of the entire OSD screen. These registers are NOT memory mapped to RAM locations. CPU access these registers by writing to the OSD data registers, row register and column register.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD) Data Sheet 283
On-Screen Display (OSD)
18.8.3.1 Window Registers 1, 2, 3, 4 Four background windows are available, with each window controlled by a set of three registers in row 15. Window 1 has the highest priority, and window 4 the least. If window over-lapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlapped window area. If the row/column start address is greater than the end address, that window will not be displayed.
COLUMN ROW 15 Window 1 Registers Window 2 Registers Window 3 Registers Window 4 Registers 0 1 2 3 4 5 6 7 8 9 10 11
Row 15, Column 0, 3, 6, 9:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROW START ADDRESS MSB LSB
ROW END ADDRESS MSB LSB
Row 15, Column 1, 4, 7, 10:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 WEN 1 0 W_SHD
COLUMN START ADDRESS MSB LSB
Row 15, Column 2, 5, 6, 11:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 R 1 G 0 B
COLUMN END ADDRESS MSB LSB
WEN -- Background Window Enable Set this bit to enable background window generation 1 = Enable background window 0 = Disable background window
Data Sheet 284 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Registers
W_SHD -- Shadow on Window Set this bit to activate the window shadowing. When the window is active, the right M pixels and lower N horizontal scan lines will output shadowing. The M, N, and color of window shadow is defined in the frame control registers located at row 15, column 16, 17, 18, and 19. See 18.8.3.5 Frame Control Registers for details. 1 = Background window shadow enabled 0 = Background window shadow disabled
Column start address Column end address
Row start address
WINDOW AREA N
M and N are defined in the frame control registers located at row 15, column 16 and 17. Row end address N SHADOW M M
R, G, B -- Background Window Color These bits define the color of the background window. 18.8.3.2 Vertical Delay Control Register Row 15, Column 12:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VERTD MSB LSB
VERTD --Vertical Delay These bits define the vertical starting position. The 8-bit gives 256 steps, with each step increment of four horizontal lines for each field. Its value cannot be zero at anytime. In order to avoid screen misalignment, the value of VERTD is decided by the last OSD line not over the next leading edge of PVSYNC.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD) Data Sheet 285
On-Screen Display (OSD)
18.8.3.3 Horizontal Delay Control Register Row 15, Column 13:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HORD MSB LSB
HORD -- Horizontal Delay These bits define the horizontal starting position for character display. The 8-bit gives 256 steps, with each step increment of six dots shift to the right on the monitor screen. The maximum value of HORD is decided by the rightmost character not exceeding the next leading edge of PHSYNC. 18.8.3.4 Character Height Control Register This register controls the height of all displayed characters. Row 15, Column 14:
15 14 13 12 11 10 9 8 7 6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0
CH[3:0] -- Expand Characters by BRM Algorithm These bits expand the 16-line characters using the binary rate multiplier (BRM) algorithm. See Figure 18-13 for some examples. CH[5:4] -- Display Character Height Select These two bits define the final height for the display characters. See Figure 18-14 for illustration.
CH5:CH4 00 or 01 10 11 Character Display Size Display size is same size as expanded font by CH[3:0]. The default value is 00. Display size is double size of expanded font by CH[3:0]. Display size is triple size of expanded font by CH[3:0].
Data Sheet 286 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Registers
NOTE:
To avoid undesirable on-screen displays, such as jittering and characters wrapping to the top, care should be taken when implementing character height expansion and vertical starting position -- ensure the last line of row14 does not exceed the PVSYNC pulse of the next frame.
Characters Height Expanded by 4-bit BRM
Character in Font Memory 12 x 16 matrix CH[3:0] = $0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 Lines
CH[3:0] = $6
22 Lines
CH[3:0] = $9
25 Lines
CH[3:0] = $F
31 Lines
Figure 18-13. Character Font Matrix Height Expansion by CH[3:0]
3x
48 to 93 lines
2x
32 to 62 lines
1x
16 to 31 lines
CH[5:4] = 0:0 or 0:1
CH[5:4] = 1:0
CH[5:4] = 1:1
Figure 18-14. Display Character Height
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD) Data Sheet 287
On-Screen Display (OSD)
18.8.3.5 Frame Control Registers Row 15, Column 15:
15 14 13 12 11 10 9 8 7
OSD_EN
6
5
4
3
2
1
0
VPOL HPOL
OSD_EN -- OSD Enable Set this bit to enable the OSD module output pins, OSDR, OSDG, OSDB, and FBKG. When OSD_EN is clear, all OSD output pins are high impedance. This bit is cleared after a POR, reset, or when OSDRST bit (bit-5 in OSD control register) is set. 1 = OSD output pins: OSDR, OSDG, OSDB, FBKG enabled 0 = OSD output pins held at high impedance HPOL -- Horizontal Sync Polarity This bit selects the polarity of the incoming horizontal sync signal on PHSYNC pin. If sync signal is negative polarity, clear this bit. If sync signal is positive polarity, set this bit. This bit is cleared after a POR, reset, or when OSDRST bit is set. 1 = Set for positive horizontal sync signal 0 = Clear for negative horizontal sync VPOL -- Vertical Sync Polarity This bit selects the polarity of the incoming vertical sync signal on PVSYNC pin. If sync signal is negative polarity, clear this bit. If sync signal is positive polarity, set this bit. This bit is cleared after a POR, reset, or when OSDRST bit is set. 1 = Set for positive vertical sync signal 0 = Clear for negative vertical sync
Data Sheet 288 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Registers
Row 15, Column 16 and 17 registers control the width and height of the shadow windows.
WINDOW AREA N
N SHADOW M M
Row 15, Column 16:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WW41 WW40 WW31 WW30 WW21 WW20 WW11 WW10
WWx1, WWx0 -- Shadow Window Width Control Bits These bits selects the width, M, for the respective enabled shadow window; where x is the window number. Table 18-1. Shadow Width Setting
WWx1:WWx0 00 01 10 11 Shadow Width M (unit in Pixels) 2 4 6 8
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
Data Sheet 289
On-Screen Display (OSD)
Row 15, Column 17:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WH41 WH40 WH31 WH30 WH21 WH20 WH11 WH10
WHx1, WHx0 -- Shadow Window Height Control Bits These bits selects the width, N, for the respective enabled shadow window; where x is the window number. Table 18-2. Shadow Width Setting
WH41:WH40 00 01 10 11 Shadow Height N (unit in Lines) 2 4 6 8
Row 15, Column 18 and 19 registers control the color of the shadow windows. Row 15, Column 18:
15 14 13 12 11 10 9 8 7 6 R1 5 G1 4 B1 3 2 R2 1 G2 0 B2
Row 15, Column 19:
15 14 13 12 11 10 9 8 7 6 R3 5 G3 4 B3 3 2 R4 1 G4 0 B4
Rx, Gx, Bx -- Shadow Window Color These bits define the color of the corresponding shadow window; where x is the window number
Data Sheet 290 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
On-Screen Display (OSD) OSD Registers
NOTE:
The width of bottom side shadowing is counted in numbers of columns and is aligned with the character width (12 dots or 16 dots) of the following row. Therefore it is possible to have misalignment of this shadowing while different character formats are used by the last row inside the window and first row outside the window. The window shadowing width of row 14 is determined by number of columns of window times 12 dots. Row 15, Column 20:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSPACE MSB LSB 1 0
RSPACE -- Row Spacing These bits define the spacing between the display rows, in units of horizontal scan lines. Due to the non-uniform expansion of the BRM algorithm used for character height control, this register is normally used for maintaining a constant OSD menu height for different display modes, instead of adjusting the character heights. The default value is 0, i.e. no extra lines inserted between. Row 15, Column 21:
15 14 13 12 11 10 9 8 7 PGE 6 5 4 3 2 1 0
PGR PGG PGB
PGE -- Screen Video Pattern Enable Set this bit to enable the free-running full-screen video pattern. Reset clears this bit. 1 = Screen video pattern enabled 0 = Screen video pattern disabled PGR, PGG, PGB -- Screen Video Pattern Color These bits define the color of the free-running full-screen video pattern.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor On-Screen Display (OSD)
Data Sheet 291
On-Screen Display (OSD)
Data Sheet 292 On-Screen Display (OSD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 19. Input/Output (I/O) Ports
19.1 Contents
19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
19.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 298 19.3.3 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 19.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.4.3 Port B Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.3 Port C Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.6.3 Port D Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.7.3 Port E Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 293
Input/Output (I/O) Ports 19.2 Introduction
Thirty-nine (39) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Bit 7 Read: PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Addr.
Register Name Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Read:
$0000
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 DDRB6 0 DDRA5 0 DDRB5 0 DDRA4 0 DDRB4 0 DDRA3 0 DDRB3 0 DDRA2 0 DDRB2 0 DDRA1 0 DDRB1 0 DDRA0 0 DDRB0 0
$0004
DDRA7 Data Direction Register A Write: (DDRA) Reset: 0 Read: DDRB7 Data Direction Register B Write: (DDRB) Reset: 0
$0005
= Unimplemented
Figure 19-1. Port I/O Register Summary
Data Sheet 294 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Introduction
Addr.
Register Name Read: Data Direction Register C Write: (DDRC) Reset: Read:
Bit 7 0
6 DDRC6
5 DDRC5 0 DDRD5 0 PTE5
4 DDRC4 0 DDRD4 0 PTE4
3 DDRC3 0 DDRD3 0 PTE3
2 DDRC2 0 DDRD2 0 PTE2
1 DDRC1 0 DDRD1 0 PTE1
Bit 0 DDRC0 0 DDRD0 0 PTE0
$0006
0
0 DDRD6 0 PTE6
$0007
DDRD7 Data Direction Register D Write: (DDRD) Reset: 0 Read: Port E Data Register Write: (PTE) Reset: Read: PTE7
$0008
Unaffected by reset DDRE6 0 KBIE6 0 DDRE5 0 KBIE5 0 DDRE4 0 KBIE4 0 R DDRE3 0 KBIE3 0 DDRE2 0 KBIE2 0 DDRE1 0 KBIE1 0 DDRE0 0 KBIE0 0
$0009
DDRE7 Data Direction Register E Write: (DDRE) Reset: 0 KBIE7 0
Read: Keyboard Interrupt Enable $004F Register Write: (KBIER) Reset: Read: $0068 Port-E Control Register Write: (PECR) Reset: Read: $0069
USBDS4E USBDS3E USBDS2E USBDS1E 0 0 VOUTE 0 PWM2E 0 0 DEE 0 PWM1E 0 0 DCLKE 0 PWM0E 0
IICDATE Port-D Control Register Write: (PDCR) Reset: 0 Read: PWM7E PWM Control Register Write: (PWMCR) Reset: 0
IICSCLE DDCDATE DDCSCLE HOUTE 0 PWM6E 0 0 PWM5E 0 0 PWM4E 0 0 PWM3E 0
$0078
= Unimplemented
Figure 19-1. Port I/O Register Summary (Continued)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 295
Input/Output (I/O) Ports
Table 19-1. Port Control Register Bits Summary
Port Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 DDRE5 DDRE6 DDRE7 Module Module Control Register Control Bit KBIE0 KBIE1 KBIE2 KBIE3 KBIER $004F KBIE4 KBIE5 KBIE6 KBIE7 PWM0E PWM1E PWM2E PWM3E PWMCR $0078 PWM4E PWM5E PWM6E PWM7E Pin PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 PTA6/KBI6 PTA7/KBI7 PTB0/PWM0 PTB1/PWM1 PTB2/PWM2 PTB3/PWM3 PTB4/PWM4 PTB5/PWM5 PTB6/PWM6 PTB7/PWM7 PTC0/ADC0 PTC1/ADC1 PTC2/ADC2 PTC3/ADC3 PTC4/ADC4 PTC5/ADC5 PTC6 PTD0/DCLK PTD1/DE PTD2/VOUT PTD3/HOUT PTD4/DDCSCL PTD5/DDCSDA PTD6/IICSCL PTD7/IICSDA PTE0/DPLUS1 PTE1/DMINUS1 PTE2/DPLUS2 PTE3/DMINUS2 PTE4/DPLUS3 PTE5/DMINUS3 PTE6/DPLUS4 PTE7/DMINUS4
A
KBI
B
PWM
C
ADC
ADSCR $003B
ADCH[4:0]
--
--
SYNC PDCR $0069
D
DDC12AB MMIIC
-- DCLKE DEE VOUTE HOUTE DDCSCLE DDCDATE IICSCLE IICDATE USBDS1E USBDS2E USBDS3E USBDS4E
E
USB
PECR $0068
Data Sheet 296 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port A
19.3 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt module (KBI). (See Section 21. Keyboard Interrupt Module (KBI).)
19.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address: $0000 Bit 7 Read: PTA7 Write: Reset: Alternative Function: KBI7 KBI6 KBI5 Unaffected by reset KBI4 KBI3 KBI2 KBI1 KBI0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 6 5 4 3 2 1 Bit 0
Figure 19-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[7:0] -- Keyboard Interrupt Pins The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt enable register (KBIER), enable the port A pins as external interrupt pins. (See 19.3.3 Port A Options and Section 21. Keyboard Interrupt Module (KBI).)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 297
Input/Output (I/O) Ports
19.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004 Bit 7 Read: DDRA7 Write: Reset: 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0
Figure 19-3. Data Direction Register A (DDRA) DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 19-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 19-4. Port A I/O Circuit
Data Sheet 298 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port A
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 19-2 summarizes the operation of the port A pins. Table 19-2. Port A Pin Functions
DDRA Bit Accesses to DDRA PTA Bit I/O Pin Mode Read/Write Read Write Accesses to PTA
0 1
X(1) X
Input, Hi-Z(2) Output
DDRA[7:0] DDRA[7:0]
Pin PTA[7:0]
PTA[7:0](3) PTA[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
19.3.3 Port A Options The keyboard interrupt enable register (KBIER) selects the port A pins for keyboard interrupt function or as standard I/O function. (See Section 21. Keyboard Interrupt Module (KBI).)
Address: $004F Bit 7 Read: KBIE7 Write: Reset: 0 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 6 5 4 3 2 1 Bit 0
Figure 19-5. Keyboard Interrupt Enable Register (KIER) KBIE[7:0] -- Keyboard Interrupt Enable Bits Setting a KBIEx bit to logic 1 configures the PTAx/KBIx pin for keyboard interrupt function. Reset clears the KBIEx bits. 1 = PTAx/KBIx pin configured as KBIx interrupt pin 0 = PTAx/KBIx pin configured as PTAx standard I/O pin
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 299
Input/Output (I/O) Ports 19.4 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the pulse width modulator (PWM). (See Section 12. Pulse Width Modulator (PWM).)
19.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins.
Address: $0001 Bit 7 Read: PTB7 Write: Reset: Alternative Function: PWM7 PWM6 PWM5 Unaffected by reset PWM4 PWM3 PWM2 PWM1 PWM0 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 6 5 4 3 2 1 Bit 0
Figure 19-6. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software-programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. PWM[7:0] -- PWM Outputs Pins The PWM output enable bits PWM7E-PWM0E, in the PWM control register (PWMCR) enable port B pins as PWM output pins. (See 19.4.3 Port B Options and Section 12. Pulse Width Modulator (PWM).)
Data Sheet 300 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port B
19.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005 Bit 7 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 6 5 4 3 2 1 Bit 0
Figure 19-7. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 19-8 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
Figure 19-8. Port B I/O Circuit
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 301
Input/Output (I/O) Ports
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 19-3 summarizes the operation of the port B pins. Table 19-3. Port B Pin Functions
DDRB Bit Accesses to DDRB PTB Bit I/O Pin Mode Read/Write Read Write Accesses to PTB
0 1
X(1) X
Input, Hi-Z(2) Output
DDRB[7:0] DDRB[7:0]
Pin PTB[7:0]
PTB[7:0](3) PTB[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
19.4.3 Port B Options The PWM control register (PWMCR) selects the port B pins for PWM function or as standard I/O function. (See Section 12. Pulse Width Modulator (PWM).)
Address: $0078 Bit 7 Read: PWM7E Write: Reset: 0 0 0 0 0 0 0 0 PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E 6 5 4 3 2 1 Bit 0
Figure 19-9. PWM Control Register (PWMCR) PWM7E-PWM0E -- PWM Output Enable Bits Setting a PWMxE bit to logic 1 configures the PTBx/PWMx pin for PWM output function. Reset clears the PWMxE bits. 1 = PTBx/PWMx pin configured as PWMx interrupt pin 0 = PTBx/PWMx pin configured as PTBx standard I/O pin
Data Sheet 302 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port C
19.5 Port C
Port C is an 7-bit special-function port that shares six of its pins with the analog-to-digital converter (ADC) module. (See Section 13. Analog-toDigital Converter (ADC).)
19.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins.
Address: $0002 Bit 7 Read: Write: Reset: Alternative Function: ADC5 = Unimplemented Unaffected by reset ADC4 ADC3 ADC2 ADC1 ADC0 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 6 5 4 3 2 1 Bit 0
Figure 19-10. Port C Data Register (PTC) PTC[6:0] -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. ADC[5:0] -- Analog-to-Digital Input Pins ADC[5:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC Status and Control Register define which port C pin will be used as an ADC input and overrides any control from the port I/O logic. (See 19.5.3 Port C Options and Section 13. Analog-to-Digital Converter (ADC).)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 303
Input/Output (I/O) Ports
NOTE:
Care must be taken when reading port C while applying analog voltages to ADC5-ADC0 pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTCx/ADCx pin, while PTC is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports.
19.5.2 Data Direction Register C Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 19-11. Data Direction Register C (DDRC) DDRC[6:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[6:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 19-12 shows the port C I/O logic.
Data Sheet 304 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port C
READ DDRC ($0006)
WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 19-12. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 19-4 summarizes the operation of the port C pins. Table 19-4. Port C Pin Functions
DDRC Bit Accesses to DDRC PTC Bit I/O Pin Mode Read/Write Read Write Accesses to PTC
0 1
X(1) X
Input, Hi-Z(2) Output
DDRC[6:0] DDRC[6:0]
Pin PTC[6:0]
PTC[6:0](3)
PTC[6:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
19.5.3 Port C Options The ADCH[4:0] bits in the ADC Status and Control Register defines which PTCx/ADCx pin is used as an ADC input and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry. (See Section 13. Analog-to-Digital Converter (ADC).)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 305
Input/Output (I/O) Ports 19.6 Port D
Port D is an 8-bit special-function port that shares two of its pins with the multi-master IIC (MMIIC) module, two of its pins with the DDC12AB module, and four of its pins with the sync processor. 19.6.1 Port D Data Register The port D data register (PTD) contains a data latch for each of the eight port D pins.
Address: $0003 Bit 7 Read: PTD7 Write: Reset: Alternative Function: IICSDA IICSCL Unaffected by reset DDCSDA DDCSCL HOUT VOUT DE DCLK PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 6 5 4 3 2 1 Bit 0
Figure 19-13. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits These read/write bits are software-programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. IICSDA, IICSCL -- Multi-master IIC Data and Clock pins The PTD7/IICSDA and PTD6/IICSCL pins are multi-master IIC data and clock pins. When the IICDATE and IICSCLE bits in the port D control register (PDCR) are clear, the PTD7/IICSDA and PTD6/IICSCL pins are available for general-purpose I/O. (See 19.6.3 Port D Options.) DDCSCL, DDCSDA -- DDC12AB Data and Clock pins The PTD4/DDCSCL and PTD5/DDCSDA pins are DDC12AB clock and data pins respectively. When the DDCSCLE and DDCDATE bits in the port D control register (PDCR) are clear, the PTD4/DDCSCL and PTD5/DDCSDA pins are available for general-purpose I/O. (See 19.6.3 Port D Options.)
Data Sheet 306 Input/Output (I/O) Ports MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port D
HOUT-- Sync Processor HOUT Pulse Output Pin The PTD3/HOUT pin is the sync processor HOUT pulse output pin. When the HOUTE bit in the port D control register (PDCR) is clear, the PTD3/HOUT pin is available for general-purpose I/O. (See 19.6.3 Port D Options.) VOUT -- Sync Processor VOUT Pulse Output Pin The PTD2/VOUT pin is the sync processor VOUT pulse output pin. When the VOUTE bit in the port D control register (PDCR) is clear, the PTD2/VOUT pin is available for general-purpose I/O. (See 19.6.3 Port D Options.) DE -- Sync Processor DE Pulse Output Pin The PTD1/DE pin is the sync processor DE pulse output pin. When the DEE bit in the port D control register (PDCR) is clear, the PTD1/DE pin is available for general-purpose I/O. (See 19.6.3 Port D Options.) DCLK -- Sync Processor DCLK Pulse Output Pin The PTD0/DCLK pin is the sync processor DCLK pulse output pin. When the DCLKE bit in the port D control register (PDCR) is clear, the PTD0/DCLK pin is available for general-purpose I/O. (See 19.6.3 Port D Options.)
19.6.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007 Bit 7 Read: DDRD7 Write: Reset: 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 6 5 4 3 2 1 Bit 0
Figure 19-14. Data Direction Register D (DDRD)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 307
Input/Output (I/O) Ports
DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 19-15 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
Figure 19-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 19-5 summarizes the operation of the port D pins. Table 19-5. Port D Pin Functions
DDRD Bit 0 1 PTD Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRD Read/Write DDRD[7:0] DDRD[7:0] Accesses to PTD Read Pin PTD[7:0] Write PTD[7:0](3) PTD[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
Data Sheet 308 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port D
19.6.3 Port D Options The port D control register (PDCR) selects the port D pins for module function or as standard I/O function.
Address: $0069 Bit 7 Read: IICDATE Write: Reset: 0 0 0 0 0 0 0 0 IICSCLE DDCDATE DDCSCLE HOUTE VOUTE DEE DCLKE 6 5 4 3 2 1 Bit 0
Figure 19-16. Port D Control Register (PDCR) IICDATE -- MMIIC Data Pin Enable This bit is set to configure the PTD7/IICSDA pin for IICSDA function. Reset clears this bit. 1 = PTD7/IICSDA pin configured as IICSDA pin 0 = PTD7/IICSDA pin configured as standard I/O pin IICSCLE -- MMIIC Clock Pin Enable This bit is set to configure the PTD6/IICSCL pin for IICSCL function. Reset clears this bit. 1 = PTD6/IICSCL pin configured as IICSCL pin 0 = PTD6/IICSCL pin configured as standard I/O pin DDCDATE -- DDC Data Pin Enable This bit is set to configure the PTD5/DDCSDA pin for DDCSDA function. Reset clears this bit. 1 = PTD5/DDCSDA pin configured as DDCSDA pin 0 = PTD5/DDCSDA pin configured as standard I/O port DDCSCLE -- DDC Clock Pin Enable This bit is set to configure the PTD4/DDCSCL pin for DDCSCL function. Reset clears this bit. 1 = PTD4/DDCSCL pin configured as DDCSCL pin 0 = PTD4/DDCSCL pin configured as standard I/O port
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 309
Input/Output (I/O) Ports
HOUTE -- HOUT Pin Enable This bit is set to configure the PTD3/HOUT pin for sync processor HOUT output. Reset clears this bit. 1 = PTD3/HOUT pin configured as HOUT pin 0 = PTD3/HOUT pin configured as standard I/O pin VOUTE -- VOUT Pin Enable This bit is set to configure the PTD2/VOUT pin for sync processor VOUT output. Reset clears this bit. 1 = PTD2/VOUT pin configured as VOUT pin 0 = PTD2/VOUT pin configured as standard I/O pin DEE -- DE Pin Enable This bit is set to configure the PTD1/DE pin for sync processor DE output. Reset clears this bit. 1 = PTD1/DE pin configured as DE pin 0 = PTD1/DE pin configured as standard I/O pin DCLKE -- DCLK Pin Enable This bit is set to configure the PTD0/DCLK pin for sync processor DCLK output. Reset clears this bit. 1 = PTD0/DCLK pin configured as DCLK pin 0 = PTD0/DCLK pin configured as standard I/O pin
Data Sheet 310 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port E
19.7 Port E
Port E is an 8-bit special-function port that shares all of its pins with the universal serial bus module. (See Section 14. Universal Serial Bus Module (USB).)
19.7.1 Port E Data Register The port E data register (PTE) contains a data latch for each of the eight port E pins.
Address: $0008 Bit 7 Read: PTE7 Write: Reset: Unaffected by reset PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 6 5 4 3 2 1 Bit 0
Alternative Function: DMINUS4 DPLUS4 DMINUS3 DPLUS3 DMINUS2 DPLUS2 DMINUS1 DPLUS1
Figure 19-17. Port E Data Register (PTE) PTE[7:0] -- Port E Data Bits These read/write bits are software-programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port E data. DPLUSx and DMINUSx -- Downstream Pairs of USB HUB Data Pins The DPLUSx and DMINUSx pins are the data pin pairs of the universal serial bus HUB. When the USBDSxE bit in the port E control register (PECR) is clear, the corresponding PTE/DPLUSx and PTE/DMINUSx pins are available for general-purpose I/O. (See 19.7.3 Port E Options.).
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports
Data Sheet 311
Input/Output (I/O) Ports
19.7.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: $0009 Bit 7 Read: DDRE7 Write: Reset: 0 0 0 0 0 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 6 5 4 3 2 1 Bit 0
Figure 19-18. Data Direction Register E (DDRE) DDRE[7:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 19-19 shows the port E I/O logic.
READ DDRE ($0009)
WRITE DDRE ($0009) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 19-19. Port E I/O Circuit
Data Sheet 312 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Input/Output (I/O) Ports Port E
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 19-6 summarizes the operation of the port E pins. Table 19-6. Port E Pin Functions
DDRE Bit 0 1 PTE Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRE Read/Write DDRE[7:0] DDRE[7:0] Accesses to PTD Read Pin PTE[7:0] Write PTE[7:0](3) PTE[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
19.7.3 Port E Options The Port E control register (PECR) selects the port E pins for USB module function or as standard I/O function.
Address: $0068 Bit 7 Read: R Write: Reset: = Unimplemented 0 0 0 0 USBDS4E USBDS3E USBDS2E USBDS1E 6 5 4 3 2 1 Bit 0
Figure 19-20. Port E Control Register (PECR) USBDS4E-USBDS1E -- USB HUB Data Pins Enable Setting a USBDSxE bit to logic 1 configures the corresponding PTE/DPLUSx and PTE/DMINUSx pins for USB HUB downstream port function. Reset clears the USBDSxE bits. 1 = PTE/DPLUSx and PTE/DMINUSx pins configured as USB pins 0 = PTE/DPLUSx and PTE/DMINUSx pins configured as standard I/O pins
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 313
Input/Output (I/O) Ports
Data Sheet 314 Input/Output (I/O) Ports
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 20. External Interrupt (IRQ)
20.1 Contents
20.2 20.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 20.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.5 20.6 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 319 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 320
20.2 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
20.3 Features
Features of the IRQ module include the following: * * * * * * A dedicated external interrupt pin, IRQ IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Internal pull-up resistor
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor External Interrupt (IRQ)
Data Sheet 315
External Interrupt (IRQ) 20.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 20-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears the interrupt latch.
*
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or falling-edge and low-leveltriggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear.
Data Sheet 316 External Interrupt (IRQ)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
External Interrupt (IRQ) Functional Description
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 9.6 Exception Control.)
ACK RESET INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD
INTERNAL
PULL-UP DEVICE
TO CPU FOR BIL/BIH INSTRUCTIONS
VDD D CLR Q SYNCHRONIZER
IRQF
IRQ
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 20-1. IRQ Module Block Diagram
Addr. Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Bit 7 0 6 0 5 0 4 0 3 IRQF 2 0 ACK 0 0 0 0 0 0 1 IMASK 0 Bit 0 MODE 0
$001E
= Unimplemented
Figure 20-2. IRQ I/O Register Summary
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor External Interrupt (IRQ)
Data Sheet 317
External Interrupt (IRQ)
20.4.1 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic 1 -- As long as the IRQ pin is at logic 0, IRQ remains active.
*
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.
MC68HC908LD64 -- Rev. 3.0 External Interrupt (IRQ) Freescale Semiconductor
Data Sheet 318
External Interrupt (IRQ) IRQ Status and Control Register (INTSCR)
20.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: * * * *
Address:
Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ interrupt pin
$001E Bit 7 6 0 5 0 4 0 3 IRQF 2 0 IMASK MODE 0 ACK 0 0 0 0 0 0 0 1 Bit 0
Read: Write: Reset:
0
= Unimplemented
Figure 20-3. IRQ Status and Control Register (INTSCR) IRQF -- IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor External Interrupt (IRQ) Data Sheet 319
External Interrupt (IRQ) 20.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 9. System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
Data Sheet 320 External Interrupt (IRQ)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 21. Keyboard Interrupt Module (KBI)
21.1 Contents
21.2 21.3 21.4 21.5 21.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
21.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 326 21.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 327 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.9 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 328
21.2 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7. When a port pin is enabled for keyboard interrupt function, an internal pull-up device is also enabled on the pin.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Keyboard Interrupt Module (KBI)
Data Sheet 321
Keyboard Interrupt Module (KBI) 21.3 Features
Features of the keyboard interrupt module (KBI) include: * * * *
Addr. $004E Register Name Keyboard Status and Read: Control Register Write: (KBSCR) Reset:
Eight keyboard interrupt pins with pull-up devices Separate keyboard interrupt enable bits and one keyboard interrupt mask Programmable edge-only or edge- and level- interrupt sensitivity Exit from low-lower modes
Bit 7 0 0 KBIE7 0 6 0 0 KBIE6 0 5 0 0 KBIE5 0 4 0 0 KBIE4 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
Keyboard Interrupt Enable Read: $004F Register Write: (KBIER) Reset:
= Unimplemented
Figure 21-1. KBI I/O Register Summary
21.4 I/O Pins
The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 21-1. The generic pin name appear in the text that follows. Table 21-1. Pin Name Conventions
KBI Generic Pin Name KBI0-KBI7 Full MCU Pin Name PTA0/KBI0-PTA7/KBI7 Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE0-KBIE7
Data Sheet 322 Keyboard Interrupt Module (KBI)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Keyboard Interrupt Module (KBI) Functional Description
21.5 Functional Description
INTERNAL BUS
KBI0 VDD . KBIE0 TO PULL-UP ENABLE . KBI7 . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request
CK
KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE7 TO PULL-UP ENABLE
Figure 21-2. Keyboard Interrupt Module Block Diagram Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pull-up device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low.
*
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request:
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Keyboard Interrupt Module (KBI) Data Sheet 323
Keyboard Interrupt Module (KBI)
* Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE2 and $FFE3. Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
MC68HC908LD64 -- Rev. 3.0 Keyboard Interrupt Module (KBI) Freescale Semiconductor
Data Sheet 324
Keyboard Interrupt Module (KBI) Keyboard Initialization
21.6 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the pull-up device to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
21.7 I/O Registers
These registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Keyboard Interrupt Module (KBI)
Data Sheet 325
Keyboard Interrupt Module (KBI)
21.7.1 Keyboard Status and Control Register * * * *
Address:
Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
$004E Bit 7 6 0 5 0 4 0 3 KEYF 2 0 IMASKK MODEK 0 ACKK 0 0 0 0 0 0 0 1 Bit 0
Read: Write: Reset:
0
= Unimplemented
Figure 21-3. Keyboard Status and Control Register (KBSCR) KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
Data Sheet 326 Keyboard Interrupt Module (KBI) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Keyboard Interrupt Module (KBI) Low-Power Modes
21.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin.
Address: $004F Bit 7 Read: KBIE7 Write: Reset: 0 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 6 5 4 3 2 1 Bit 0
Figure 21-4. Keyboard Interrupt Enable Register (KBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx/KBIx pin enabled as keyboard interrupt pin 0 = PTAx/KBIx pin not enabled as keyboard interrupt pin
21.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
21.8.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
21.8.2 Stop Mode The keyboard interrupt module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Keyboard Interrupt Module (KBI)
Data Sheet 327
Keyboard Interrupt Module (KBI) 21.9 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See 21.7.1 Keyboard Status and Control Register.)
Data Sheet 328 Keyboard Interrupt Module (KBI)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 22. Computer Operating Properly (COP)
22.1 Contents
22.2 22.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
22.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 332 22.5 22.6 22.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
22.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 334
22.2 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Computer Operating Properly (COP) Data Sheet 329
Computer Operating Properly (COP) 22.3 Functional Description
Figure 22-1 shows the structure of the COP module.
OSCXCLK
12-BIT COP PRESCALER CLEAR ALL STAGES CLEAR STAGES 5-12
RESET CIRCUIT RESET STATUS REGISTER
STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE
COP CLOCK
6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG)
CLEAR COP COUNTER
Figure 22-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 OSCXCLK cycles, depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 218 - 24 OSCXCLK cycle overflow option, a 24MHz crystal gives a COP timeout period of 10.922ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow.
Data Sheet 330 Computer Operating Properly (COP)
COP TIMEOUT
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Computer Operating Properly (COP) I/O Signals
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state, VTST on the RST pin disables the COP.
NOTE:
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
22.4 I/O Signals
The following paragraphs describe the signals shown in Figure 22-1.
22.4.1 OSCXCLK OSCXCLK is the crystal oscillator output signal. OSCXCLK frequency is equal to the crystal frequency.
22.4.2 STOP Instruction The STOP instruction clears the COP prescaler.
22.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 22.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector.
22.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 OSCXCLK cycles after power-up.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Computer Operating Properly (COP)
Data Sheet 331
Computer Operating Properly (COP)
22.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 22.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 22.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG register. (See Figure 22-2.) 22.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG register. (See Figure 22-2.)
Address: $001F Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 SSREC COPRS STOP COPD 3 2 1 Bit 0
= Unimplemented
Figure 22-2. Configuration Register (CONFIG) COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is 213 - 24 OSCXCLK cycles 0 = COP timeout period is 218 - 24 OSCXCLK cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
Data Sheet 332 Computer Operating Properly (COP)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Computer Operating Properly (COP) COP Control Register
22.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address:
$FFFF Bit 7 6 5 4 3 2 1 Bit 0
Read: Write: Reset:
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 22-3. COP Control Register (COPCTL)
22.6 Interrupts
The COP does not generate CPU interrupt requests.
22.7 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
22.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Computer Operating Properly (COP)
Data Sheet 333
Computer Operating Properly (COP)
22.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
22.8.2 Stop Mode Stop mode turns off the OSCXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
22.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
Data Sheet 334 Computer Operating Properly (COP)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 23. Break Module (BRK)
23.1 Contents
23.2 23.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 338 23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .338 23.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 338 23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 338 23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 339 23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 342
23.2 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Break Module (BRK)
Data Sheet 335
Break Module (BRK) 23.3 Features
Features of the break module include: * * * * Accessible input/output (I/O) registers during the break interrupt CPU-generated break interrupts Software-generated break interrupts COP disabling during break interrupts
23.4 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 23-1 shows the structure of the break module.
Data Sheet 336 Break Module (BRK)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Break Module (BRK) Functional Description
IAB15-IAB8
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15-IAB0 CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK
IAB7-IAB0
Figure 23-1. Break Module Block Diagram
Addr.
Register Name
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW Note 0
Bit 0 R
Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Break Flag Control Write: Register (SBFCR) Reset: Read: Break Address Register Write: High (BRKH) Reset: Read: Break Address Register Write: Low (BRKL) Reset:
$FE03
BCFE 0 Bit 15 0 Bit 7 0 BRKE 0
R
R
R
R
R
R
R
$FE0C
14 0 6 0 BRKA 0
13 0 5 0 0
12 0 4 0 0
11 0 3 0 0
10 0 2 0 0
9 0 1 0 0
Bit 8 0 Bit 0 0 0
$FE0D
Read: Break Status and Control $FE0E Write: Register (BRKSCR) Reset:
Note: Writing a logic 0 clears SBSW.
0
0
0 R
0 = Reserved
0
0
= Unimplemented
Figure 23-2. Break Module I/O Register Summary
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Break Module (BRK)
Data Sheet 337
Break Module (BRK)
23.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state.
23.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
23.4.3 TIM During Break Interrupts A break interrupt stops the timer counters.
23.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin.
23.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
23.5.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see Section 9. System Integration Module (SIM)). Clear the SBSW bit by writing logic 0 to it.
Data Sheet 338 Break Module (BRK) MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Break Module (BRK) Break Module Registers
23.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
23.6 Break Module Registers
These registers control and monitor operation of the break module: * * * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) SIM break status register (SBSR) SIM break flag control register (SBFCR)
23.6.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0E Bit 7 Read: BRKE Write: Reset: 0 0 0 0 0 0 0 0 BRKA 6 5 0 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 23-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Break Module (BRK)
Data Sheet 339
Break Module (BRK)
BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match
23.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Figure 23-4. Break Address Register High (BRKH)
Address: $FE0D Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 23-5. Break Address Register Low (BRKL)
23.6.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
Data Sheet 340 Break Module (BRK)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Break Module (BRK) Break Module Registers
Address:
$FE00 Bit 7 6 R 5 R 4 R 3 R 2 R Note 0 R = Reserved 1 SBSW R R Bit 0
Read: Write: Reset:
Note: Writing a logic 0 clears SBSW.
Figure 23-6. SIM Break Status Register (SBSR) SBSW -- SIM Break Stop/Wait Bit This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Break Module (BRK)
Data Sheet 341
Break Module (BRK)
23.6.4 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: BCFE Write: Reset: 0 R = Reserved R R R R R R R 6 5 4 3 2 1 Bit 0
Figure 23-7. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Data Sheet 342 Break Module (BRK)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 24. Electrical Specifications
24.1 Contents
24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 345 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 346 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 347 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
24.10 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 348 24.11 Sync Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.12 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 349 24.12.1 USB Low Speed Source Electrical Characteristics . . . . . . 350 24.12.2 USB High Speed Source Electrical Characteristics . . . . . . 351 24.12.3 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . 352 24.12.4 USB Signaling Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24.13 DDC12AB/MMIIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 24.13.1 DDC12AB/MMIIC Interface Input Signal Timing . . . . . . . . 354 24.13.2 DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . 354 24.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 355
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 343
Electrical Specifications 24.2 Introduction
This section contains electrical and timing specifications.
24.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 24.6 DC Electrical Characteristics for guaranteed operating conditions. Table 24-1. Absolute Maximum Ratings
Characteristic(1) Supply voltage Input voltage Input voltage, +5V pins IICSDA, IICSCL, DDCSDA, DCSCL, HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK Maximum current per pin excluding VDD and VSS Storage temperature Maximum current out of VSS Maximum current into VDD
Notes: 1. Voltages referenced to VSS.
Symbol VDD VIN
Value -0.3 to +3.9 VSS -0.3 to VDD +0.3
Unit V V
VHIN
VSS -0.3 to +5.5
V
I TSTG IMVSS IMVDD
25 -55 to +150 80 80
mA C mA mA
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
Data Sheet 344 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications Functional Operating Range
24.4 Functional Operating Range
Table 24-2. Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value 0 to +85 3.0 to 3.6 Unit C V
24.5 Thermal Characteristics
Table 24-3. Thermal Characteristics
Characteristic Thermal resistance QFP (64 pins) I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature Maximum junction temperature Symbol JA PI/O PD K TJ TJM Value 70 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) 100 Unit C/W W W
W/C C C
Notes: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 345
Electrical Specifications 24.6 DC Electrical Characteristics
Table 24-4. DC Electrical Characteristics
Characteristic(1) Output high voltage (ILOAD = -2.0mA) All output pins Output low voltage (ILOAD = 1.6mA) All output pins Input high voltage All ports (except PTD4-PTD7), IRQ, RST, OSC1 For +5V rated pins HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK, IICSDA, IICSCL, DDCSDA, DDCSCL Input low voltage All ports (except PTD4-PTD7), IRQ, RST, OSC1 For +5V rated pins HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK, IICSDA, IICSCL, DDCSDA, DDCSCL VDD supply current Run, USB active, PLL on, fOP = 6.0 MHz(3) Run, USB suspended, PLL off, fOP = 6.0 MHz(3) Wait, USB active, PLL on, fOP = 6.0 MHz(4) Wait, USB suspended, PLL off, fOP = 6.0 MHz(4) Stop(5) 0C to +85C I/O ports Hi-Z leakage current Input current All input pins (except below pins) HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK Capacitance Ports (as input or output) POR re-arm voltage(6) POR rise time ramp rate
(7)
Symbol VOH VOL
Min 2.4 --
Typ(2) -- --
Max -- 0.4
Unit V V
VIH
0.7 x VDD 2.0
-- --
VDD 5.5
V
VIL
VSS VSS -- -- -- -- -- -- -- -- -- -- 0 0.035 VDD + 1.7 30
-- -- 11 9 6 4 100 -- -- -- -- -- -- -- -- 45 2.45 2.6
0.2 x VDD 0.8 20 16 12 8 200 10 1 2 12 8 100 -- 6 60
V
IDD
mA mA mA mA A A A pF mV V/ms V k V V
IIL IIN COUT CIN VPOR RPOR VTST RPU VTRIPF VTRIPR VHYS
Monitor mode entry voltage Pull-up resistor: KBI0-KBI7, RST, IRQ Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recover hysteresis
--
150
--
mV
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOSCXCLK = 24MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; USB in suspend mode, 15k 5% termination resistors on D+ and D- pins; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. STOP IDD measured with USB in suspend mode, OSC1 grounded, 1.5k 1% pull-up resistor on D+ pin and 15k 1% pulldown resistors on D+ and D- pins, no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
Data Sheet 346 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications Control Timing
24.7 Control Timing
Table 24-5. Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 50 Max 6 -- Unit MHz ns
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
24.8 TImer Interface Module Characteristics
Table 24-6. TIM Characteristics
Characteristic Input capture pulse width Input clock pulse width Symbol tTIH, tTIL tTCH, tTCL Min 125 (1/fOP) + 5 Max -- -- Unit ns ns
24.9 Oscillator Characteristics
Table 24-7. Oscillator Characteristics
Characteristic Crystal frequency(1) External clock Reference frequency(1), (2) Crystal fixed capacitance(3) Crystal tuning capacitance(3) Feedback bias resistor Series resistor(3) Symbol fOSCXCLK fOSCXCLK C1 C2 RB RS Min -- dc -- -- -- -- Typ 24 24 15 15 2 0 Max -- -- -- -- -- -- Unit MHz MHz pF pF M
Notes: 1. The sync processor module is designed to function at fOSCXCLK = 24MHz. 2. No more than 10% duty cycle deviation from 50% 3. Not Required for high frequency crystals
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 347
Electrical Specifications 24.10 ADC Electrical Characteristics
Table 24-8. ADC Electrical Characteristics
Characteristic(1) Supply voltage Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(2) Zero input reading(3) Full-scale reading(3) Input capacitance Input leakage(4) Port C Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI -- Min 3.0 0 8 1 0.5 VSS 16 16 5 00 FD -- -- 17 -- 02 FF 8 1 Max 3.6 VDD 8 2 1.048 VDD Unit V V Bits LSB MHz V tAIC cycles tAIC cycles tAIC cycles HEX HEX pF A Not tested Includes quantization tAIC = 1/fADIC, tested only at 1 MHz Comments VDD 10%
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
Data Sheet 348 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications Sync Processor Timing
24.11 Sync Processor Timing
Table 24-9. Sync Processor Timing
Characteristic(1) VSYNC input sync pulse HSYNC input sync pulse VSYNC to VSYNCO delay (8pF loading) HSYNC to HSYNCO delay (8pF loading) DE set-up time of DCLK DE hold time of DCLK Symbol tVI.SP tHI.SP tVVd tHHd tDESu tDEHd Min 8 0.1 30 30 4 4 Max 2048 6 40 40 -- -- Unit s s s s s s
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
24.12 USB DC Electrical Characteristics
Table 24-10. USB DC Electrical Characteristics
Characteristic(1) Hi-Z state data line leakage Differential input sensitivity Differential common mode range Single ended receiver threshold Static output low Static output high Symbol ILO VDI VCM VSE VOL VOH RL of 1.5k to 3.6V RL of 15k to GND 2.8 Conditions 0VNotes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 349
Electrical Specifications
24.12.1 USB Low Speed Source Electrical Characteristics Table 24-11. USB Low Speed Source Electrical Characteristics
Characteristic Internal operating frequency Transition time(2) Rise time Fall time Rise/Fall time matching Output signal crossover voltage Low speed data rate Source differential driver jitter To next transition For paired transitions Receiver data jitter tolerance To next transition For paired transitions Source EOP width Differential to EOP transition skew Receiver EOP width Must reject as EOP Must accept Symbol fOP TR TF TRFM VCRS TDRATE 1.5Mbs 1.5% CL=200pF CL=600pF CL=200pF CL=600pF TR/TF 75 75 80 1.3 1.4775 676.8 -25 -10 1.500 666.0 Conditions(1) Min Typ 6 -- 300 -- 300 -- 120 2.0 1.5225 656.8 25 10 Max Unit MHz ns ns ns ns % V Mbs ns ns ns
TUDJ1 TUDJ2 TDJR1 TDJR2 TEOPT TDEOP TEOPR1 TEOPR2
CL=350pF Note (3), (4) CL=350pF Notes (3), (4) Note (4) Note (4)
-75 -45 1.25 -40 330 675
75 45 1.50 100
ns ns s ns ns ns
Note (4)
Notes: 1. All voltages measured from local ground, unless otherwise specified. All timings use a capacitive load of 50pF, unless otherwise specified. Low speed timings have a 1.5k pull-up to 2.8V on the D- data line. 2. Transitions are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50pF of tester capacitance. 3. Timing differences between the differential data signals. 4. Measured at crossover point of differential data signals.
Data Sheet 350 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications USB DC Electrical Characteristics
24.12.2 USB High Speed Source Electrical Characteristics Table 24-12. USB High Speed Source Electrical Characteristics
Characteristic Internal operating frequency Transition time(2) Rise time Fall time Rise/Fall time matching Output signal crossover voltage High speed data rate Frame interval Source differential driver jitter To next transition For paired transitions Source EOP Width Differential to EOP transition skew Receive data jitter tolerance To next transition For paired transitions Receiver EOP width Must reject as EOP Must accept Symbol fOP TR TF TRFM VCRS TDRATE TFRAME TDJ1 TDJ1 TEOPT TDEOP TJR1 TJR2 TEOPR1 TEOPR2 12Mbs 0.25% 1.0ms 0.05% CL=50pF Notes (3), (4) Note (4) Note (4) CL=50pF Notes (3), (4) CL=50pF CL=50pF TR/TF 4 4 90 1.3 11.97 0.9995 -3.5 -4.0 160 -2 -18.5 -9 40 82 Conditions(1) Min Typ 6 20 20 110 2.0 12.03 1.0005 3.5 4.0 175 5 18.5 9 Max Unit MHz ns ns % V Mbs ms ns ns ns ns ns ns ns ns
Note (4)
Notes: 1. All voltages measured from local ground, unless otherwise specified. All timings use a capacitive load of 50pF, unless otherwise specified. High speed timings have a 1.5k pull-up to 2.8V on the D+ data line. 2. Transitions are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50pF of tester capacitance. 3. Timing differences between the differential data signals. 4. Measured at crossover point of differential data signals.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 351
Electrical Specifications
24.12.3 HUB Repeater Electrical Characteristics Table 24-13. HUB Repeater Electrical Characteristics Low Speed HUB Electrical Characteristics (Root port and downstream ports configured as low speed)
Characteristic HUB differential data delay HUB differential driver jitter (including cable) Downstream: To next transition For paired transitions Upstream To next transition For paired transitions Data bit width distortion after EOP. HUB EOP delay relative to THDD HUB EOP output width skew Symbol TLHDD Conditions Note(1),(2),(3) Note (4),(5),(6) Min Typ Max 300 Unit ns
TLDHJ1 TLDHJ2 TLUHJ1 TLUHJ2 TEOP TLEOPD TLHESK
Note (4),(5),(6)
-45 -15 45 45
45 15 45 45 60 200 300
ns ns ns ns ns ns ns
Note (4),(6) Note (4),(6) Note (4),(6)
-60 0 -300
Full Speed HUB Electrical Characteristics (Root port and downstream ports configured as full speed)
Characteristic HUB differential data delay (with cable) (without cable) HUB differential driver jitter (including cable) To next transition For paired transitions Data bit width distortion after SOP HUB EOP delay relative to THDD HUB EOP output width skew Symbol Conditions (Notes 1,2,3) Note (3),(5),(6) Min Typ Max Unit
THDD1 THDD1
70 40
ns ns
THDJ1 THDJ2 TSOP TEOPD THESK
Note (3),(5),(6)
-3 -1 -5 0 -15
3 1 5 15 15
ns ns ns ns ns
Note (3),(6) Note (3),(6) Note (3),(6)
Notes: 1. All voltages measured from local ground, unless otherwise specified. 2. All timings use a capacitive load of (CL) to ground of 50pF, unless otherwise specified. 3. Full speed timings have a 1.5k pull-up to 2.8V on the D+ data line. 4. Low speed timings have a 1.5k pull-up to 2.8V on the D- data line. 5. Timing differences between the differential data signals. 6. Measured at crossover point of differential data signals. Measured from 10% to 90% of the data signal.
The rising and falling edges should be smoothly transitioning (monotonic). The maximum load specification is the maximum effective capacitive load allowed that meets the target HUB VBUS droop of 330mV.
Data Sheet 352 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications USB DC Electrical Characteristics
24.12.4 USB Signaling Levels Table 24-14. USB Signaling Levels
Signaling Levels Bus State From Originating Driver Differential "1" Differential "0" Data J State: Low Speed Full Speed Data K State: Low Speed Full Speed Idle State: Low Speed Full Speed Resume State: Low Speed Full Speed Start of Packet (SOP) End of Packet (EOP) Disconnect (Upstream only) Connect (Upstream only) Reset (Downstream only)
Notes:
At Receiver
(D+) - (D-) > 200 mV and D+ or D- > VSE (min.) (D+) - (D-) < -200 mV and D+ or D- > VSE (min.) Differential "0" Differential "1" Differential "1" Differential "0" Differential "0" and D- > VSE (max.) and D+ < VSE (min.) Differential "1" and D+ > VSE (max.) and D- < VSE (min.) Differential "1" and D+ > VSE (max.) and D- < VSE (min.) Differential "0" and D- > VSE (max.) and D+ < VSE (min.) Data lines switch from Idle to K State D+ and D- < VSE (min) for 2 bit times(1) followed by an Idle for 1 bit time -- -- D+ and D- < VSE(min) for 1 bit time(2) followed by a J State D+ and D- < VSE(max) for 2.5 s D+ or D- > VSE(max) for 2.5 s D+ and D- < VSE (min) for 2.5 s (must be recognized within 5.5 s)(3)
D+ and D- < VSE for 10 ms
1. The width of EOP is defined in bit times relative to the speed of transmission. 2. The width of EOP is defined in bit times relative to the device type receiving the EOP. 3. These times apply to an active device that is not in the suspend state.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 353
Electrical Specifications 24.13 DDC12AB/MMIIC Timing
SDA
SCL
tHD.STA
tLOW
tHIGH
tSU.DAT
tHD.DAT
tSU.STA
tSU.STO
Figure 24-1. MMIIC Signal Timings 24.13.1 DDC12AB/MMIIC Interface Input Signal Timing Table 24-15. DDC12AB/MMIIC Interface Input Signal Timing
Characteristic(1) START condition hold time Clock low period Clock high period Data set-up time Data hold time START condition set-up time (for repeated START condition only) STOP condition set-up time Symbol tHD.STA tLOW tHIGH tSU.DAT tHD.DAT tSU.STA tSU.STO Min 2 4 4 250 0 2 2 Max -- -- -- -- -- -- -- Unit tCYC tCYC tCYC ns ns tCYC tCYC
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
24.13.2 DDC12AB/MMIIC Interface Output Signal Timing Table 24-16. DDC12AB/MMIIC Interface Output Signal Timing
Characteristic(1) SDA/SCL rise time(2) SDA/SCL fall time Data set-up time Data hold time Symbol tR tF tSU.DAT tHD.DAT Min -- -- tLOW 0 Max 1 300 -- -- Unit s ns ns ns
Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. With 200pF loading on the SDA/SCL pins.
Data Sheet 354 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Electrical Specifications FLASH Memory Characteristics
24.14 FLASH Memory Characteristics
Table 24-17. FLASH Memory Electrical Characteristics
Characteristic Program bus clock frequency FLASH block size $0C00-$0FFF $1000-F9FF FLASH programming size Read bus clock frequency Page erase time Mass erase time PGM/ERASE to HVEN set up time High-voltage hold time High-voltage hold time (mass erase) Program hold time Program time Return to read time Cumulative program HV period 4,7616 bytes array 13K-bytes array Row erase endurance(7) Row program endurance Data retention time(9)
(8)
Symbol -- -- -- -- fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvhl tpgs tPROG trcv(4) tHV(5) tHV1
(6)
Min 1 128 512 64 32k 10 10 5 5 100 20 20 1
Max --
Unit MHz Bytes Bytes Bytes
6M -- -- -- -- -- -- 40 --
Hz ms ms s s s ns s s
-- -- 10k 10k 10
6 3 -- -- --
ms ms Cycles Cycles Years
-- -- --
Notes: 1. fREAD is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG x 64) tHV max. 6. tHV1 is the tHV spec for 13K-bytes array 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 9. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Electrical Specifications
Data Sheet 355
Electrical Specifications
Data Sheet 356 Electrical Specifications
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 25. Mechanical Specifications
25.1 Contents
25.2 25.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 64-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 358
25.2 Introduction
This section gives the dimensions for: * 64-pin plastic quad flat pack (case #840B)
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Mechanical Specifications
Data Sheet 357
Mechanical Specifications 25.3 64-Pin Plastic Quad Flat Pack (QFP)
L
48 49 33 32 S S
D
D
0.05 (0.002) A-B
B B P
S
C A-B
-A- L
-B- B
V
M
0.20 (0.008)
0.20 (0.008)
M
H A-B
S
-A-, -B-, -D-
DETAIL A
DETAIL A
64 17
1
F
16
-D- A 0.20 (0.008)
M
C A-B
S
D
S
J
N
0.05 (0.002) A-B S 0.20 (0.008) M H A-B E
S
D M
S
D DETAILC 0.02 (0.008)
M
BASE METAL
C A-B
S
D
S
C -C-
SEATING PLANE
-H- H M G
DATUM PLANE
SECTION B-B
0.01 (0.004)
U T R -H-
DATUM PLANE
Q K W X DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) PER SIDE. TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.30 0.45 2.00 2.40 0.30 0.40 0.80 BSC -- 0.25 0.13 0.23 0.65 0.95 12.00 REF 5 10 0.13 0.17 0.40 BSC 0 7 0.13 0.30 16.95 17.45 0.13 -- 0 -- 16.95 17.45 0.35 0.45 1.6 REF
INCHES MIN MAX 0.547 0.555 0.547 0.555 0.085 0.096 0.012 0.018 0.079 0.094 0.012 0.016 0.031 BSC -- 0.010 0.005 0.009 0.026 0.037 0.472 REF 5 10 0.005 0.007 0.016 BSC 0 7 0.005 0.012 0.667 0.687 0.005 -- 0 -- 0.667 0.687 0.014 0.018 0.063 REF
Figure 25-1. 64-Pin QFP (Case #840B)
Data Sheet 358 Mechanical Specifications MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
Data Sheet -- MC68HC908LD64
Section 26. Ordering Information
26.1 Contents
26.2 26.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
26.2 Introduction
This section contains ordering numbers for the MC68HC908LD64.
26.3 MC Order Numbers
Table 26-1. MC Order Numbers
MC Order Number(1)
MC68HC908LD64IFU
Package
64-Pin QFP
Operating Temperature Range 0 C to +85 C
Notes: 1. I = Operating temperature range: 0 C to +85 C FU = Quad Flat Pack
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor Ordering Information
Data Sheet 359
Ordering Information
Data Sheet 360 Ordering Information
MC68HC908LD64 -- Rev. 3.0 Freescale Semiconductor
How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 Home Page: www.freescale.com
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Learn More: For more information about Freescale products, please visit www.freescale.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004 MC68HC908LD64 Rev. 3 07/2004

▲Up To Search▲

Price & Availability of MC68HC908LD64

	To Download MC68HC908LD64 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .